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A25L080Q4-UFG 参数 Datasheet PDF下载

A25L080Q4-UFG图片预览
型号: A25L080Q4-UFG
PDF下载: 下载PDF文件 查看货源
内容描述: 16Mbit的低电压,串行闪存的100MHz统一4KB扇区 [16Mbit Low Voltage, Serial Flash Memory With 100MHz Uniform 4KB Sectors]
分类和应用: 闪存
文件页数/大小: 43 页 / 681 K
品牌: AMICC [ AMIC TECHNOLOGY ]
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A25L016 Series  
Read Status Register (RDSR)  
The Read Status Register (RDSR) instruction allows the  
Status Register to be read. The Status Register may be read  
at any time, even while a Program, Erase or Write Status  
Register cycle is in progress. When one of these cycles is in  
progress, it is recommended to check the Write In Progress  
(WIP) bit before sending a new instruction to the device. It is  
also possible to read the Status Register continuously, as  
shown in Figure 6.  
reset to 0 no such cycle is in progress.  
WEL bit. The Write Enable Latch (WEL) bit indicates the  
status of the internal Write Enable Latch. When set to 1 the  
internal Write Enable Latch is set, when set to 0 the internal  
Write Enable Latch is reset and no Write Status Register,  
Program or Erase instruction is accepted.  
BP2, BP1, BP0 bits. The Block Protect (BP2, BP1, BP0) bits  
are non-volatile. They define the size of the area to be  
software protected against Program and Erase instructions.  
These bits are written with the Write Status Register (WRSR)  
instruction. When one or more of the Block Protect (BP2,  
BP1, BP0) bits is set to 1, the relevant memory area (as  
defined in Table 1.) becomes protected against Page  
Program (PP), Sector Erase (SE), and Block Erase (BE)  
instructions. The Block Protect (BP2, BP1, BP0) bits can be  
written provided that the Hardware Protected mode has not  
been set. The Chip Erase (CE) instruction is executed if, and  
only if, all Block Protect (BP2, BP1, BP0) bits are 0.  
Table 4. Status Register Format  
b7  
SRWD  
b6  
0
b5  
0
b4  
b3  
b2  
b1  
b0  
BP2 BP1 BP0 WEL WIP  
Status Register  
Write Protect  
Block Protect Bits  
SRWD bit. The Status Register Write Disable (SRWD) bit is  
Write Enable Latch Bit  
Write In Progress Bit  
operated in conjunction with the Write Protect ( ) signal.  
W
The Status Register Write Disable (SRWD) bit and Write  
Protect (  
) signal allow the device to be put in the  
W
Hardware Protected mode (when the Status Register Write  
The status and control bits of the Status Register are as  
follows:  
WIP bit. The Write In Progress (WIP) bit indicates whether  
the memory is busy with a Write Status Register, Program or  
Erase cycle. When set to 1, such a cycle is in progress, when  
Disable (SRWD) bit is set to 1, and Write Protect ( ) is  
W
driven Low). In this mode, the non-volatile bits of the Status  
Register (SRWD, BP2, BP1, BP0) become read-only bits and  
the Write Status Register (WRSR) instruction is no longer  
accepted for execution.  
Figure 6. Read Status Register (RDSR) Instruction Sequence and Data-Out Sequence  
S
0
1
2
3
4
5
6
7
8
9 10 11 12  
14 15  
13  
C
Instruction  
DIO  
Status Register Out  
Status Register Out  
High Impedance  
DO  
5
7
6
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB  
MSB  
(March, 2012, Version 2.0)  
12  
AMIC Technology Corp.  
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