P R E L I M I N A R Y
Figure 21. Back-to-back Read/Write Cycle Timings ....................... 50
Figure 30. SRAM Write Cycle—WE# Control ................................ 58
Figure 31. SRAM Write Cycle—CE1#s Control ............................. 59
Figure 32. SRAM Write Cycle—UB#s and LB#s Control............... 60
Flash Erase And Programming Performance ........................ 61
Flash Latchup Characteristics. . . . . . . . . . . . . . . 61
Package Pin Capacitance . . . . . . . . . . . . . . . . . . 61
Flash Data Retention . . . . . . . . . . . . . . . . . . . . . . 61
SRAM Data Retention . . . . . . . . . . . . . . . . . . . . . 62
Figure 33. CE1#s Controlled Data Retention Mode....................... 62
Figure 34. CE2s Controlled Data Retention Mode......................... 62
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 63
FLB073—73-Ball Fine-Pitch Grid Array 8 x 11.6 mm .............63
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 64
Revision A (October 25, 2001) ...............................................64
Revision A+1 (September 5, 2002) ........................................64
Figure 22. Data# Polling Timings (During Embedded Algorithms).. 50
Figure 23. Toggle Bit Timings (During Embedded Algorithms)....... 51
Figure 24. DQ2 vs. DQ6.................................................................. 51
Temporary Sector/Sector Block Unprotect ............................. 52
Figure 25. Temporary Sector/Sector Block Unprotect
Timing Diagram............................................................................... 52
Figure 26. Sector/Sector Block Protect and Unprotect
Timing Diagram............................................................................... 53
Alternate CE#f Controlled Erase and Program Operations .... 54
Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program) Op-
eration Timings................................................................................ 55
SRAM Read Cycle ..................................................................56
Figure 28. SRAM Read Cycle—Address Controlled....................... 56
Figure 29. SRAM Read Cycle......................................................... 57
SRAM Write Cycle ..................................................................58
4
Am41DL32x8G
September 5, 2002
AMD [ AMD ]
