P R E L I M I N A R Y
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
MCP Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . 5
Flash Memory Block Diagram. . . . . . . . . . . . . . . . 6
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7
Special Handling Instructions for FBGA Package .................... 7
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 10
Table 2. Device Bus Operations—Flash Word Mode, CIOf = V
SRAM Byte Mode, CIOs = V
SS
......................................................12
Table 3. Device Bus Operations—Flash Byte Mode, CIOf = V
SRAM Word Mode, CIOs = V
CC
.....................................................13
Table 4. Device Bus Operations—Flash Byte Mode, CIOf = V
Byte Mode, CIOs = V
SS
..................................................................14
Command Definitions . . . . . . . . . . . . . . . . . . . . . 28
Reading Array Data ................................................................ 28
Reset Command ..................................................................... 28
Autoselect Command Sequence ............................................ 28
Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 29
Byte/Word Program Command Sequence ............................. 29
Chip Erase Command Sequence ........................................... 30
Sector Erase Command Sequence ........................................ 30
Erase Suspend/Erase Resume Commands ........................... 31
Word/Byte Configuration ........................................................ 15
Requirements for Reading Array Data ................................... 15
Writing Commands/Command Sequences ............................ 15
Simultaneous Read/Write Operations with Zero Latency ....... 15
Standby Mode ........................................................................ 16
Automatic Sleep Mode ........................................................... 16
RESET#: Hardware Reset Pin ............................................... 16
Output Disable Mode .............................................................. 16
Bottom Boot SecSi Sector Addresses ........................................ 20
Write Operation Status . . . . . . . . . . . . . . . . . . . . 34
DQ7: Data# Polling ................................................................. 34
RY/BY#: Ready/Busy# ............................................................ 35
DQ6: Toggle Bit I .................................................................... 35
Figure 6. Toggle Bit Algorithm........................................................ 35
DQ2: Toggle Bit II ................................................................... 36
Reading Toggle Bits DQ6/DQ2 ............................................... 36
DQ5: Exceeded Timing Limits ................................................ 36
DQ3: Sector Erase Timer ....................................................... 36
Autoselect Mode ..................................................................... 21
Sector/Sector Block Protection and Unprotection .................. 21
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 38
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 38
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 39
CMOS Compatible .................................................................. 39
SRAM DC and Operating Characteristics . . . . . 40
Zero-Power Flash ................................................................. 41
Figure 10. Typical I
CC1
vs. Frequency............................................ 41
Write Protect (WP#) ................................................................ 22
Temporary Sector/Sector Block Unprotect ............................. 22
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 11. Test Setup.................................................................... 42
Key To Switching Waveforms . . . . . . . . . . . . . . . 42
SecSi (Secured Silicon) Sector Flash Memory Region .......... 24
Hardware Data Protection ...................................................... 24
Logical Inhibit ...................................................................... 24
Common Flash Memory Interface (CFI) . . . . . . . 25
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 43
SRAM CE#s Timing ................................................................ 43
Flash Read-Only Operations ................................................. 44
Hardware Reset (RESET#) .................................................... 45
Flash Word/Byte Configuration (CIOf) .................................... 46
Flash Erase and Program Operations .................................... 47
September 5, 2002
Am41DL32x8G
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