P R E L I M I N A R Y
PIN DESCRIPTION
A18–A0
= 19 Address Inputs (Common)
A-1, A20–A19 = 3 Address Inputs (Flash)
SA
DQ15–DQ0
CE#f
CE#s
OE#
WE#
RY/BY#
UB#s
LB#s
CIOf
= Highest Order Address Pin (SRAM)
Byte mode
= 16 Data Inputs/Outputs (Common)
= Chip Enable (Flash)
= Chip Enable (SRAM)
= Output Enable (Common)
= Write Enable (Common)
= Ready/Busy Output
= Upper Byte Control (SRAM)
= Lower Byte Control (SRAM)
= I/O Configuration (Flash)
CIOf = V
IH
= Word mode (x16),
CIOf = V
IL
= Byte mode (x8)
= I/O Configuration (SRAM)
CIOs = V
IH
= Word mode (x16),
CIOs = V
IL
= Byte mode (x8)
= Hardware Reset Pin, Active Low
= Hardware Write Protect/
Acceleration Pin (Flash)
= Flash 3.0 volt-only single power sup-
ply (see Product Selector Guide for
speed options and voltage supply
tolerances)
= SRAM Power Supply
= Device Ground (Common)
= Pin Not Connected Internally
LOGIC SYMBOL
19
A18–A0
A-1, A20–A19
SA
CE#f
CE1#s
CE2s
OE#
WE#
WP#/ACC
RESET#
UB#s
LB#s
CIOf
CIOs
RY/BY#
DQ15–DQ0
16 or 8
CIOs
RESET#
WP#/ACC
V
CC
f
V
CC
s
V
SS
NC
8
Am41DL32x8G
September 5, 2002
AMD [ ADVANCED MICRO DEVICES ]
