P R E L I M I N A R Y
Notes:
1. The I
CC
current listed is typically less than 2 mA/MHz, with OE# at V
IH
.
2. Maximum I
CC
specifications are tested with V
CC
= V
CC
max.
3. I
CC
active while Embedded Erase or Embedded Program is in progress.
4. Automatic sleep mode enables the low power mode when addresses remain stable for t
ACC
+ 30 ns. Typical sleep mode current is
200 nA.
5. Not 100% tested.
SRAM DC AND OPERATING CHARACTERISTICS
Parameter
Symbol
I
LI
I
LO
I
CC
Parameter Description
Input Leakage Current
Output Leakage Current
Operating Power Supply Current
Test Conditions
V
IN
= V
SS
to V
CC
CE1#s = V
IH
, CE2s = V
IL
or OE# =
V
IH
or WE# = V
IL
, V
IO
= V
SS
to V
CC
I
IO
= 0 mA, CE1#s = V
IL
, CE2s =
WE# = V
IH
, V
IN
= V
IH
or V
IL
Cycle time = 1 µs, 100% duty,
I
IO
= 0 mA, CE1#s
≤
0.2 V,
CE2
≥
V
CC
– 0.2 V, V
IN
≤
0.2 V or
V
IN
≥
V
CC
– 0.2 V
Cycle time = Min., I
IO
= 0 mA,
100% duty, CE1#s = V
IL
, CE2s =
V
IH
, V
IN
= V
IL
= or V
IH
I
OL
= 2.1 mA
I
OH
= –1.0 mA
CE1#s = V
IH
, CE2 = V
IL
, Other
inputs = V
IH
or V
IL
CE1#s
≥
V
CC
– 0.2 V, CE2
≥
V
CC
–
0.2 V (CE1#s controlled) or CE2
≤
0.2 V (CE2s controlled), CIOs =
V
SS
or V
CC
, Other input = 0 ~ V
CC
2.4
0.3
Min
–1.0
–1.0
Typ
Max
1.0
1.0
3
Unit
µA
µA
mA
I
CC1
s
Average Operating Current
3
mA
I
CC2
s
V
OL
V
OH
I
SB
Average Operating Current
Output Low Voltage
Output High Voltage
Standby Current (TTL)
30
0.4
mA
V
V
mA
I
SB1
Standby Current (CMOS)
15
µA
40
Am41DL32x8G
September 5, 2002