P R E L I M I N A R Y
TEST CONDITIONS
Table 21. Test Specifications
Test Condition 70, 85 ns
3.3 V
Unit
Output Load
1 TTL gate
2.7 kΩ
Device
Under
Test
Output Load Capacitance, CL
(including jig capacitance)
30
pF
Input Rise and Fall Times
Input Pulse Levels
5
ns
V
C
L
6.2 kΩ
0.0–3.0
Input timing measurement reference
levels
1.5
1.5
V
V
Output timing measurement
reference levels
Note: Diodes are IN3064 or equivalent
Figure 11. Test Setup
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Center Line is High Impedance State (High Z)
KS000010-PAL
2.0 V
0.0 V
1.0 V
1.0 V
Input
Measurement Level
Output
Figure 12. Input Waveforms and Measurement Levels
42
Am41DL32x8G
September 5, 2002