P R E L I M I N A R Y
AC CHARACTERISTICS
Flash Read-Only Operations
Parameter
Speed Options
Test Setup
Unit
JEDEC
tAVAV
Std
tRC
tACC
tCE
Description
70
70
70
70
30
85
85
85
85
40
Read Cycle Time (Note 1)
Min
CE#f, OE# = VIL Max
ns
ns
ns
ns
ns
ns
tAVQV
tELQV
tGLQV
tEHQZ
tGHQZ
Address to Output Delay
Chip Enable to Output Delay
Output Enable to Output Delay
Chip Enable to Output High Z (Note 1)
Output Enable to Output High Z (Note 1)
OE# = VIL
Max
Max
Max
Max
tOE
tDF
16
16
tDF
Output Hold Time From Addresses, CE#f or
OE#, Whichever Occurs First
tAXQX
tOH
Min
Min
Min
0
0
ns
ns
ns
Read
Output Enable Hold Time
tOEH
Toggle and
Data# Polling
(Note 1)
10
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 21 for test specifications.
tRC
Addresses Stable
tACC
Addresses
CE#f
tRH
tRH
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
Output Valid
HIGH Z
HIGH Z
Outputs
RESET#
RY/BY#
0 V
Figure 14. Read Operation Timings
44
Am41DL32x8G
September 5, 2002
AMD [ AMD ]
