P R E L I M I N A R Y
Table 20. Write Operation Status
DQ7
(Note 2)
DQ5
(Note 1)
DQ2
(Note 2)
Status
DQ6
DQ3
RY/BY#
Embedded Program Algorithm
Embedded Erase Algorithm
Erase
DQ7#
0
Toggle
Toggle
0
0
N/A
1
No toggle
Toggle
0
0
Standard
Mode
1
No toggle
0
N/A
Toggle
1
Suspended Sector
Erase-Suspend-
Read
Erase
Suspend
Mode
Non-Erase
Data
Data
Data
0
Data
N/A
Data
N/A
1
0
Suspended Sector
Erase-Suspend-Program
DQ7#
Toggle
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
Refer to the section on DQ5 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further
details.
3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm
is in progress. The device outputs array data if the system addresses a non-busy bank.
September 5, 2002
Am41DL32x8G
37
AMD [ AMD ]
