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M41000002T 参数 Datasheet PDF下载

M41000002T图片预览
型号: M41000002T
PDF下载: 下载PDF文件 查看货源
内容描述: 32兆位( 4米×8位/ 2的M× 16位) CMOS 3.0伏只,同步读/写闪存和8兆位( 1一M× 8位/ 512的K× 16位)静态RAM [32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory and 8 Mbit (1 M x 8-Bit/512 K x 16-Bit) Static RAM]
分类和应用: 闪存
文件页数/大小: 66 页 / 1128 K
品牌: AMD [ ADVANCED MICRO DEVICES ]
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P R E L I M I N A R Y
Table 18.
Command
Sequence
(Note 1)
Read (Note 6)
Reset (Note 7)
Autoselect (Note 8)
Manufacturer ID
Sector Protect Verify
(Note 10)
Command Definitions (Flash Byte Mode)
Second
Addr Data
Bus Cycles (Notes 2–5)
Third
Fourth
Addr Data Addr
Data
Fifth
Sixth
Addr Data Addr Data
Cycles
1
1
4
6
4
4
3
4
4
3
2
2
6
6
1
1
1
First
Addr Data
RA
XXX
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
XXX
XXX
AAA
AAA
BA
BA
55
RD
F0
AA
AA
AA
AA
AA
AA
AA
AA
A0
90
AA
AA
B0
30
98
555
555
555
555
555
555
555
555
PA
XXX
555
555
55
55
55
55
55
55
55
55
PD
00
55
55
(BA)
AAA
(BA)
AAA
(BA)
AAA
(BA)
AAA
AAA
AAA
AAA
AAA
90
90
90
90
88
90
A0
20
(BA) 00
(BA) 02
(BA)
X06
(SADD)
X04
XXX
PA
01
see
Table 19
82/02
00
01
00
PD
Enter SecSi Sector Region
Exit SecSi Sector Region
Program
Unlock Bypass
Unlock Bypass Program (Note 11)
Unlock Bypass Reset (Note 12)
Chip Erase
Sector Erase
Erase Suspend (Note 13)
Erase Resume (Note 14)
CFI Query (Note 15)
AAA
AAA
80
80
AAA
AAA
AA
AA
555
555
55
55
AAA
SADD
10
30
Legend:
X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses
latch on the falling edge of the WE# or CE#f pulse, whichever happens
later.
Notes:
1. See Table 1 for description of bus operations.
2.
3.
4.
5.
6.
7.
All values are in hexadecimal.
Except for the read cycle and the fourth cycle of the autoselect
command sequence, all bus cycles are write cycles.
Data bits DQ15–DQ8 are don’t care in command sequences,
except for RD and PD.
Unless otherwise noted, address bits A20–A12 are don’t cares.
No unlock or command cycles required when bank is in read
mode.
The Reset command is required to return to reading array data
(or to the erase-suspend-read mode if previously in Erase
Suspend) when a bank is in the autoselect mode, or if DQ5 goes
high (while the bank is providing status information).
The fourth cycle of the autoselect command sequence is a read
cycle. The system must provide the bank address to obtain the
manufacturer ID, device ID, or SecSi Sector factory protect
information. Data bits DQ15–DQ8 are don’t care. See the
Autoselect Command Sequence section for more information.
The data is 80h for factory locked and 00h for not factory locked.
PD = Data to be programmed at location PA. Data latches on the rising
edge of WE# or CE#f pulse, whichever happens first.
SADD = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A20–A12 uniquely select any sector.
BA = Address of the bank that is being switched to autoselect mode, is
in bypass mode, or is being erased.
11. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
12. The Unlock Bypass Reset command is required to return to
reading array data when the bank is in the unlock bypass mode.
13. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation, and requires the bank address.
14. The Erase Resume command is valid only during the Erase
Suspend mode, and requires the bank address.
15. Command is valid when device is ready to read array data or when
device is in autoselect mode.
8.
Table 19.
Device
Autoselect Device IDs (Byte Mode)
Autoselect Device ID
55h (T), 56h (B)
50h (T), 53h (B)
5Ch (T), 5Fh (B)
Am29DL322G
Am29DL323G
Am29DL324G
9.
10. The data is 00h for an unprotected sector/sector block and 01h
for a protected sector/sector block.
T = Top Boot Sector, B = Bottom Boot Sector
September 5, 2002
Am41DL32x8G
33