P R E L I M I N A R Y
Any commands written during the chip erase operation
are ignored. However, note that a
hardware reset
im-
mediately terminates the erase operation. If that
occurs, the chip erase command sequence should be
reinitiated once that bank has returned to reading
array data, to ensure data integrity.
Figure 4 illustrates the algorithm for the erase opera-
tion. Refer to the Flash Erase and Program
Operations tables in the AC Characteristics section for
param et ers, and Figu re 20 sect ion fo r tim ing
diagrams.
START
Write Program
Command Sequence
Embedded
Program
algorithm
in progress
Data Poll
from System
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two ad-
ditional unlock cycles are written, and are then
followed by the address of the sector to be erased,
and the sector erase command. Tables 16 and 18
show the address and data requirements for the sec-
tor erase command sequence.
The device does
not
require the system to preprogram
prior to erase. The Embedded Erase algorithm auto-
matically programs and verifies the entire memory for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
After the command sequence is written, a sector erase
time-out of 50 µs occurs. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time
between these additional cycles must be less than
50 µs, otherwise erasure may begin. Any sector erase
address and command following the exceeded
time-out may or may not be accepted. It is recom-
mended that processor interrupts be disabled during
this time to ensure all commands are accepted. The
interrupts can be re-enabled after the last Sector
Erase command is written.
Any command other than
Se ctor E rase or E rase Suspend dur ing the
time-out period resets that bank to reading array
data.
The system must rewrite the command se-
quence and any additional addresses and commands.
The system can monitor DQ3 to determine if the sec-
tor erase timer has timed out (See the section on DQ3:
Sector Erase Timer.). The time-out begins from the ris-
ing edge of the final WE# pulse in the command
sequence.
When the Embedded Erase algorithm is complete, the
bank returns to reading array data and addresses are
no longer latched. Note that while the Embedded
Erase operation is in progress, the system can read
data from the non-erasing bank. The system can de-
Verify Data?
No
Yes
No
Increment Address
Last Address?
Yes
Programming
Completed
Note:
See for program command sequence.
Figure 3.
Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does
not
require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Tables 16 and
18 show the address and data requirements for the
chip erase command sequence.
When the Embedded Erase algorithm is complete,
that bank returns to reading array data and addresses
are no longer latched. The system can determine the
status of the erase operation by using DQ7, DQ6,
DQ2, or RY/BY#. Refer to the Write Operation Status
section for information on these status bits.
30
Am41DL32x8G
September 5, 2002
AMD [ ADVANCED MICRO DEVICES ]
