P R E L I M I N A R Y
Table 13.
Addresses
(Word Mode)
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
Addresses
(Byte Mode)
36h
38h
3Ah
3Ch
3Eh
40h
42h
44h
46h
48h
4Ah
4Ch
Data
0027h
0036h
0000h
0000h
0004h
0000h
000Ah
0000h
0005h
0000h
0004h
0000h
System Interface String
Description
V
CC
Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
V
CC
Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
V
PP
Min. voltage (00h = no V
PP
pin present)
V
PP
Max. voltage (00h = no V
PP
pin present)
Typical timeout per single byte/word write 2
N
µs
Typical timeout for Min. size buffer write 2
N
µ
s (00h = not supported)
Typical timeout per individual block erase 2
N
ms
Typical timeout for full chip erase 2
N
ms (00h = not supported)
Max. timeout for byte/word write 2
N
times typical
Max. timeout for buffer write 2
N
times typical
Max. timeout per individual block erase 2
N
times typical
Max. timeout for full chip erase 2
N
times typical (00h = not supported)
Table 14.
Addresses
(Word Mode)
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
Addresses
(Byte Mode)
4Eh
50h
52h
54h
56h
58h
5Ah
5Ch
5Eh
60h
62h
64h
66h
68h
6Ah
6Ch
6Eh
70h
72h
74h
76h
78h
Data
0016h
0002h
0000h
0000h
0000h
0002h
0007h
0000h
0020h
0000h
003Eh
0000h
0000h
0001h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
Device Geometry Definition
Description
Device Size = 2
N
byte
Flash Device Interface description (refer to CFI publication 100)
Max. number of byte in multi-byte write = 2
N
(00h = not supported)
Number of Erase Block Regions within device
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
Erase Block Region 2 Information
Erase Block Region 3 Information
Erase Block Region 4 Information
26
Am41DL32x8G
September 5, 2002
AMD [ ADVANCED MICRO DEVICES ]
