Statistic counters are maintained and accurate during
that time.
a collision, dynamic FCS generation on a frame-by-
frame basis, automatic pad field insertion and deletion
to enforce minimum frame size attributes, automatic re-
transmission without reloading the FIFO, and auto-
matic deletion of collision fragments.
During the time that the Receive Frame Queuing
mechanism is in operation, the Am79C978 controller
relies on the Receive Poll Time Counter (CSR 48) to
control the worst case access to the RDTE. The Re-
ceive Poll Time Counter is programmed through the
Receive Polling Interval (CSR49) register. The Re-
ceived Polling Interval defaults to approximately 2 ms.
TheAm79C978 controller will also try to access the
RDTE during normal descriptor accesses whether they
are transmit or receive accesses. The host can force
the Am79C978 controller to immediately access the
RDTE by setting the RDMD (CSR 7, bit 13) to 1. Its op-
eration is similar to the transmit one. The polling pro-
cess can be disabled by setting the RXDPOLL (CSR7,
bit 12) bit. This will stop the automatic polling process
and the host must set the RDMD bit to initiate the re-
ceive process into host memory. Receive frames are
still stored even when the receive polling process is
disabled.
The two primary attributes of the MAC engine are:
n Transmit and receive message data encapsulation
— Framing (frame boundary delimitation, frame
synchronization)
— Addressing (source and destination address
handling)
— Error detection (physical medium transmission
errors)
n Media access management
— Medium allocation (collision avoidance, except
in full-duplex operation)
— Contention resolution (collision handling, except
in full-duplex operation)
Transmit and Receive Message Data
Encapsulation
Software Interrupt Timer
TheAm79C978 controller is equipped with a software
programmable free-running interrupt timer. The timer is
constantly running and will generate an interrupt STINT
(CSR 7, bit 11) when STINITE (CSR 7, bit 10) is set to
1. After generating the interrupt, the software timer will
load the value stored in STVAL and restart. The timer
value STVAL (BCR31, bits 15-0) is interpreted as an
unsigned number with a resolution of 256 Time Base
Clock periods. For instance, a value of 122 ms would
be programmed with a value of 9531 (253Bh), if the
Time Base Clock is running at 20 MHz. The default
value of STVAL is FFFFh which yields the approximate
maximum 838 ms timer duration. A write to STVAL re-
starts the timer with the new contents of STVAL.
The MAC engine provides minimum frame size en-
forcement for transmit and receive frames. When
APAD_XMT (CSR, bit 11) is set to 1, transmit mes-
sages will be padded with sufficient bytes (containing
00h) to ensure that the receiving station will observe an
information field (destination address, source address,
length/type, data, and FCS) of 64 bytes. When
ASTRP_RCV (CSR4, bit 10) is set to 1, the receiver will
automatically strip pad bytes from the received mes-
sage by observing the value in the length field and by
stripping excess bytes if this value is below the mini-
mum data size (46 bytes). Both features can be inde-
pendently over-ridden to allow illegally short (less than
64 bytes of frame data) messages to be transmitted
and/or received. The use of this feature reduces bus
utilization because the pad bytes are not transferred
into or out of main memory.
10/100 Media Access Controller
The Media Access Controller (MAC) engine incorpo-
rates the essential protocol requirements for operation
of an Ethernet/IEEE 802.3-compliant node and pro-
vides the interface between the FIFO subsystem and
the internal PHY.
Framing
The MAC engine will autonomously handle the con-
struction of the transmit frame. Once the transmit FIFO
has been filled to the predetermined threshold (set by
XMTSP in CSR80) and access to the channel is cur-
rently permitted, the MAC engine will commence the 7-
byte preamble sequence (10101010b, where first bit
transmitted is a 1). The MAC engine will subsequently
append the Start Frame Delimiter (SFD) byte
(10101011b) followed by the serialized data from the
transmit FIFO. Once the data has been completed, the
MAC engine will append the FCS (most significant bit
first), which was computed on the entire data portion of
the frame. The data portion of the frame consists of
destination address, source address, length/type, and
frame data. The user is responsible for the correct or-
This section describes operation of the MAC engine
when operating in half-duplex mode. When operating
in half-duplex mode, the MAC engine is fully compliant
to Section 4 of ISO/IEC 8802-3 (ANSI/IEEE Standard
1990 Second Edition) and ANSI/IEEE 802.3 (1985).
When operating in full-duplex mode, the MAC engine
behavior changes as described in the section Full-
Duplex Operation.
The MAC engine provides programmable enhanced
features designed to minimize host supervision, bus
utilization, and pre- or post-message processing.
These features include the ability to disable retries after
Am79C978
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