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AM79C978KC/W 参数 Datasheet PDF下载

AM79C978KC/W图片预览
型号: AM79C978KC/W
PDF下载: 下载PDF文件 查看货源
内容描述: 单芯片1/10 Mbps的PCI家庭网络控制器 [Single-Chip 1/10 Mbps PCI Home Networking Controller]
分类和应用: 控制器PC
文件页数/大小: 261 页 / 3499 K
品牌: AMD [ AMD ]
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dering and content in each of these fields in the frame.  
The MAC does not use the content in the length/type  
field unless APAD_XMT (CSR4, bit 11) is set and the  
data portion of the frame is shorter than 60 bytes.  
dicate a potentially faulty transceiver or network  
connection.  
n Late Collision (LCOL) indicates that the transmis-  
sion suffered a collision after the slot time. This is in-  
dicative of a badly configured network. Late  
collisions should not occur in a normal operating  
network.  
The MAC engine will detect the incoming preamble se-  
quence when the RX_DV signal is activated by the in-  
ternal PHY. The MAC will discard the preamble and  
begin searching for the SFD. Once the SFD is de-  
tected, all subsequent nibbles are treated as part of the  
frame. The MAC engine will inspect the length field to  
ensure minimum frame size, strip unnecessary pad  
characters (if enabled), and pass the remaining bytes  
through the receive FIFO to the host. If pad stripping is  
performed, the MAC engine will also strip the received  
FCS bytes, although normal FCS computation and  
checking will occur. Note that apart from pad stripping,  
the frame will be passed unmodified to the host. If the  
length field has a value of 46 or greater, all frame bytes  
including FCS will be passed unmodified to the receive  
buffer, regardless of the actual frame length.  
n Collision Error (CERR) indicates that the trans-  
ceiver did not respond with an SQE Test message  
within the first 4 ms after a transmission was com-  
pleted. This may be due to a failed transceiver, dis-  
connected or faulty transceiver drop cable, or  
because the transceiver does not support this fea-  
ture (or it is disabled). SQE Test is only valid for 10-  
Mbps networks.  
In addition to the reporting of network errors, the MAC  
engine will also attempt to prevent the creation of any  
network error due to the inability of the host to service  
the MAC engine. During transmission, if the host fails  
to keep the transmit FIFO filled sufficiently, causing an  
underflow, the MAC engine will guarantee the message  
is either sent as a runt packet (which will be deleted by  
the receiving station) or as an invalid FCS (which will  
also cause the receiver to reject the message).  
If the frame terminates or suffers a collision before 64  
bytes of information (after SFD) have been received,  
the MAC engine will automatically delete the frame  
from the receive FIFO, without host intervention.  
TheAm79C978 controller has the ability to accept runt  
packets for diagnostic purposes and proprietary net-  
works.  
The status of each receive message is available in the  
appropriate Receive Message Descriptor (RMD) and  
CSR areas. All received frames are passed to the host  
regardless of any error. The FRAM error will only be re-  
ported if an FCS error is detected and there is a non-  
integral number of bytes in the message.  
Destination Address Handling  
The first 6 bytes of information after SFD will be inter-  
preted as the destination address field. The MAC en-  
gine provides facilities for physical (unicast), logical  
(multicast), and broadcast address reception.  
During the reception, the FCS is generated on every  
nibble (including the dribbling bits) coming from the ca-  
ble, although the internally saved FCS value is only up-  
dated on the eighth bit (on each byte boundary). The  
MAC engine will ignore up to 7 additional bits at the end  
of a message (dribbling bits), which can occur under  
normal network operating conditions. The framing error  
is reported to the user as follows:  
Error Detection  
The MAC engine provides several facilities which re-  
port and recover from errors on the medium. In addi-  
tion, it protects the network from gross errors due to  
inability of the host to keep pace with the MAC engine  
activity.  
n If the number of dribbling bits are 1 to 7 and there is  
no FCS error, then there is no Framing error  
(FRAM = 0).  
On completion of transmission, the following transmit  
status is available in the appropriate Transmit Message  
Descriptor (TMD) and Control and Status Register  
(CSR) areas:  
n If the number of dribbling bits are 1 to 7 and there is  
a FCS error, then there is also a Framing error  
(FRAM = 1).  
n The number of transmission retry attempts (ONE,  
MORE, RTRY, and TRC).  
n If the number of dribbling bits is 0, then there is no  
Framing error. There may or may not be a FCS er-  
ror.  
n Whether the MAC engine had to Defer (DEF) due to  
channel activity.  
n Excessive deferral (EXDEF), indicating that the  
transmitter experienced Excessive Deferral on this  
transmit frame, where Excessive Deferral is defined  
in the ISO 8802-3 (IEEE/ANSI 802.3) standard.  
n If the number of dribbling bits is 8, then there is no  
Framing error. FCS error will be reported, and the  
receive message count will indicate one extra byte.  
Counters are provided to report the Receive Collision  
Count and Runt Packet Count for network statistics  
and utilization calculations.  
n Loss of Carrier (LCAR), indicating that there was an  
interruption in the ability of the MAC engine to mon-  
itor its own transmission. Repeated LCAR errors in-  
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Am79C978  
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