P R E L I M I N A R Y
RY/BY# pins can be tied together in parallel with
Table 6 shows the outputs for Toggle Bit I on
DQ6. Figure 1 shows the toggle bit algorithm.
Figure 1 in the “AC Characteristics” section
shows the toggle bit timing diagrams. Figure 1
shows the differences between DQ2 and DQ6 in
graphical form. See also the subsection on
“DQ2: Toggle Bit II”.
a pull-up resistor to VCC.
If the output is low (Busy), the device is actively
erasing or programming. (This includes pro-
gramming in the Erase Suspend mode.) If the
output is high (Ready), the device is ready to
read array data (including during the Erase
Suspend mode), or is in the standby mode.
DQ2: Toggle Bit II
Table 6 shows the outputs for RY/BY#. Figures
1, 1, 1 and 1 shows RY/BY# for read, reset, pro-
gram, and erase operations, respectively.
The “Toggle Bit II” on DQ2, when used with
DQ6, indicates whether a particular sector is
actively erasing (that is, the Embedded Erase
algorithm is in progress), or whether that sector
is erase-suspended. Toggle Bit II is valid after
the rising edge of the final WE# pulse in the
command sequence.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an
Embedded Program or Erase algorithm is in
progress or complete, or whether the device has
entered the Erase Suspend mode. Toggle Bit I
may be read at any address, and is valid after
the rising edge of the final WE# pulse in the
command sequence (prior to the program or
erase operation), and during the sector erase
time-out.
DQ2 toggles when the system reads at
addresses within those sectors that have been
selected for erasure. (The system may use
either OE# or CE# to control the read cycles.)
But DQ2 cannot distinguish whether the sector
is actively erasing or is erase-suspended. DQ6,
by comparison, indicates whether the device is
actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for
erasure. Thus, both status bits are required for
sector and mode information. Refer to Table 6 to
compare outputs for DQ2 and DQ6.
During an Embedded Program or Erase algo-
rithm operation, successive read cycles to any
address cause DQ6 to toggle. (The system may
use either OE# or CE# to control the read
cycles.) When the operation is complete, DQ6
stops toggling.
Figure 1 shows the toggle bit algorithm in flow-
chart form, and the section “DQ2: Toggle Bit II”
explains the algorithm. See also the “DQ6:
Toggle Bit I” subsection. Figure 1 shows the
toggle bit timing diagram. Figure 1 shows the
differences between DQ2 and DQ6 in graphical
form.
After an erase command sequence is written, if
all sectors selected for erasing are protected,
DQ6 toggles for approximately 100 µs, then
returns to reading array data. If not all selected
sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and
ignores the selected sectors that are protected.
Reading Toggle Bits DQ6/DQ2
The system can use DQ6 and DQ2 together to
determine whether a sector is actively erasing
or is erase-suspended. When the device is
actively erasing (that is, the Embedded Erase
algorithm is in progress), DQ6 toggles. When
the device enters the Erase Suspend mode, DQ6
stops toggling. However, the system must also
use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system
can use DQ7 (see the subsection on “DQ7:
Data# Polling”).
Refer to Figure 1 for the following discussion.
Whenever the system initially begins reading
toggle bit status, it must read DQ7–DQ0 at least
twice in a row to determine whether a toggle bit
is toggling. Typically, the system would note and
store the value of the toggle bit after the first
read. After the second read, the system would
compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device
has completed the program or erase operation.
The system can read array data on DQ7–DQ0 on
the following read cycle.
If a program address falls within a protected
sector, DQ6 toggles for approximately 1 µs after
the program command sequence is written,
then returns to reading array data.
However, if after the initial two read cycles, the
system determines that the toggle bit is still
toggling, the system also should note whether
the value of DQ5 is high (see the section on
DQ5). If it is, the system should then determine
again whether the toggle bit is toggling, since
the toggle bit may have stopped toggling just as
DQ6 also toggles during the erase-suspend-
program mode, and stops toggling once the
Embedded Program algorithm is complete.
24
Am29LV800D
Am29LV800D_00_A4_E January 21, 2005
AMD [ AMD ]
