P R E L I M I N A R Y
Word
Byte
Word
Byte
555
AAA
555
AAA
XXX
XXX
2AA
555
2AA
555
555
AAA
555
AAA
555
AAA
555
AAA
2AA
555
2AA
555
555
AAA
Chip Erase
6
6
AA
AA
55
55
80
80
AA
AA
55
55
10
30
Sector Erase
SA
Erase Suspend (Note 12)
Erase Resume (Note 13)
1
1
B0
30
Legend:
X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse,
whichever happens later.
PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens
first.
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A18–A12 uniquely select any
sector.
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles are write operations.
4. Data bits DQ15–DQ8 are don’t cares for unlock and command cycles.
5. Address bits A18–A11 are don’t cares for unlock and command cycles, unless PA or SA required.
6. No unlock or command cycles required when reading array data.
7. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5
goes high (while the device is providing status data).
8. The fourth cycle of the autoselect command sequence is a read cycle.
9. The data is 00h for an unprotected sector and 01h for a protected sector. See “Autoselect Command Sequence” for
more information.
10.The Unlock Bypass command is required prior to the Unlock Bypass Program command.
11.The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock
bypass mode.
12.The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend
mode. The Erase Suspend command is valid only during a sector erase operation.
13.The Erase Resume command is valid only during the Erase Suspend mode.
Write Operation Status
The device provides several bits to determine
the status of a write operation: DQ2, DQ3, DQ5,
DQ6, DQ7, and RY/BY#. Table 6 and the fol-
lowing subsections describe the functions of
these bits. DQ7, RY/BY#, and DQ6 each offer a
method for determining whether a program or
erase operation is complete or in progress.
These three bits are discussed first.
datum programmed to DQ7. This DQ7 status
also applies to programming during Erase Sus-
pend. When the Embedded Program algorithm
is complete, the device outputs the datum pro-
grammed to DQ7. The system must provide the
program address to read valid status informa-
tion on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active
for approximately 1 µs, then the device returns
to reading array data.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host
system whether an Embedded Algorithm is in
progress or completed, or whether the device is
in Erase Suspend. Data# Polling is valid after
the rising edge of the final WE# pulse in the
program or erase command sequence.
During the Embedded Erase algorithm, Data#
Polling produces a “0” on DQ7. When the
Embedded Erase algorithm is complete, or if the
device enters the Erase Suspend mode, Data#
Polling produces a “1” on DQ7. This is analogous
to the complement/true datum output described
for the Embedded Program algorithm: the erase
function changes all the bits in a sector to “1”;
During the Embedded Program algorithm, the
device outputs on DQ7 the complement of the
22
Am29LV800D
Am29LV800D_00_A4_E January 21, 2005
AMD [ AMD ]
