P R E L I M I N A R Y
Table 5. Am29DL800B Command Definitions
Bus Cycles (Notes 2–5)
Command
Sequence
(Note 1)
First
Second
Third
Addr
Fourth
Addr
Fifth
Sixth
Addr Data Addr Data
Data
Data Addr Data Addr Data
Read (Note 6)
Reset (Note 7)
1
1
RA
XXX
555
RD
F0
Word
Byte
Word
Byte
Word
Byte
2AA
555
2AA
555
2AA
555
(BA)555
(BA)AAA
(BA)555
(BA)AAA
(BA)555
(BA)AAA
Manufacturer ID
4
4
4
AA
AA
AA
55
55
55
90 (BA)X00
01
4A
AAA
555
(BA)X01 224A
Device ID,
Top Boot Block
90
90
AAA
555
(BA)X02
(BA)X01 22CB
Device ID,
Bottom Boot Block
AAA
(BA)X02
CB
XX00
XX01
00
(SA)
X02
Word
Byte
555
2AA
555
(BA)555
(BA)AAA
Sector Protect
Verify (Note 9)
4
AA
55
90
(SA)
X04
AAA
01
Word
Byte
Word
Byte
555
AAA
555
AAA
XXX
BA
2AA
555
2AA
555
PA
555
AAA
555
Program
4
3
AA
AA
55
55
A0
20
PA
PD
Unlock Bypass
AAA
Unlock Bypass Program (Note 10)
Unlock Bypass Reset (Note 11)
2
2
A0
90
PD
00
XXX
2AA
555
2AA
555
Word
555
AAA
555
AAA
BA
555
AAA
555
555
AAA
555
2AA
555
2AA
555
555
Chip Erase
Byte
6
6
AA
AA
55
55
80
80
AA
AA
55
55
10
30
AAA
Word
Sector Erase
Byte
SA
AAA
AAA
Erase Suspend (Note 12)
Erase Resume (Note 13)
1
1
B0
30
BA
Legend:
X = Don’t care
PD = Data to be programmed at location PA. Data latches on the
rising edge of WE# or CE# pulse, whichever happens first.
RA = Address of the memory location to be read.
SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A18–A12 uniquely select any sector.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed.
Addresses latch on the falling edge of the WE# or CE# pulse,
whichever happens later.
BA = Address of the bank that is being switched to autoselect
mode, is in bypass mode, or is being erased. Address bits A18–
A16 select a bank.
Notes:
1. See Table 1 for description of bus operations.
8. The fourth cycle of the autoselect command sequence is a
read cycle. The system must provide the bank address to
obtain the manufacturer or device ID information.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles
are write operations.
9. The data is 00h for an unprotected sector and 01h for a
protected sector. See the Autoselect Command Sequence
section for more information.
4. Data bits DQ15–DQ8 are don’t cares for unlock and command
cycles.
10. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
5. Address bits A18–A11 are don’t cares for unlock and
command cycles, unless bank address (BA) is required.
11. The Unlock Bypass Reset command is required to return to
reading array data when the bank is in the unlock bypass
mode.
6. No unlock or command cycles required when bank is in read
mode.
7. The Reset command is required to return to reading array
data (or to the erase-suspend-read mode if previously in
Erase Suspend) when a bank is in the autoselect mode, or if
DQ5 is goes high (while the bank is providing status
information).
12. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector
erase operation, and requires the bank address.
13. The Erase Resume command is valid only during the Erase
Suspend mode, and requires the bank address.
Am29DL800B
19
AMD [ AMD ]
