generation of internal voltages for margin checking and
read operations (section E).
Parallel Device Erasure
Many applications will use more than one Flash
memory device. Total erase time may be minimized by
implementing a parallel erase algorithm. Flash
memories may erase at different rates. Therefore each
device must be verified separately. When a device is
completely erased and verified use a masking code to
prevent further erasure. The other devices will continue
to erase until verified. The masking code applied could
be the read command (00h).
During program-verification (section F) each byte just
programmed is read to compare array data with original
program data. When successfully verified, the next de-
sired address is programmed. Should a byte fail to ver-
ify, reprogram the byte (repeat section A thru F). Each
data change sequence allows the device to use up to
25 program pulses per byte. Typically, bytes are verified
within one or two pulses.
Algorithm Timing Delays
Power-Up/Power-Down Sequence
There are four different timing delays associated with
the Flasherase and Flashrite algorithms:
The device powers-up in the Read only mode. Power
supply sequencing is not required. Note that if VCC
≤
1.0 Volt, the voltage difference between VPP and VCC
should not exceed 10.0 Volts. Also, the device has VPP
rise time and fall time specification of 500 ns minimum.
1. The first delay is associated with the VPP rise-time
when VPP first turns on. The capacitors on the VPP
bus cause an RC ramp. After switching on the VPP
,
the delay required is proportional to the number of
devices being erased and the 0.1 mF/device. VPP
must reach its final value 100 ns before commands
are executed.
Reset Command
The Reset command initializes the Flash memory de-
vice to the Read mode. In addition, it also provides the
user with a safe method to abort any device operation
(including program or erase).
2. The second delay time is the erase time pulse width
(10 ms). A software timing routine should be run by
the local microprocessor to time out the delay. The
erase operation must be terminated at the conclu-
sion of the timing routine or prior to executing any
system interrupts that may occur during the erase
operation. To ensure proper device operation, write
the Erase-verify operation after each pulse.
The Reset command must be written two consecutive
times after the setup Program command (40h). This will
reset the device to the Read mode.
Following any other Flash command write the Reset
command once to the device. This will safely abort any
previous operation and initialize the device to the
Read mode.
3. A third delay time is required for each programming
pulse width (10 ms). The programming algorithm is
interactive and verifies each byte after a program
pulse. The program operation must be terminated at
the conclusion of the timing routine or prior to exe-
cuting any system interrupts that may occur during
the programming operation.
The Setup Program command (40h) is the only com-
mand that requires a two sequence reset cycle. The
first Reset command is interpreted as program data.
However, FFh data is considered null data during pro-
gramming operations (memory cells are only pro-
grammed from a logical “1” to “0”). The second Reset
command safely aborts the programming operation
and resets the device to the Read mode.
4. A fourth timing delay associated with both the
Flasherase and Flashrite algorithms is the write re-
covery time (6 ms). During this time internal circuitry
is changing voltage levels from the erase/ program
level to those used for margin verify and read oper-
ations. An attempt to read the device during this pe-
riod will result in possible false data (it may appear
the device is not properly erased or programmed).
Memory contents are not altered in any case.
This detailed information is for your reference. It may
prove easier to always issue the Reset command two
consecutive times. This eliminates the need to deter-
mine if you are in the setup Program state or not.
Note: Software timing routines should be written in
machine language for each of the delays. Code written
in machine language requires knowledge of the appro-
priate microprocessor clock speed in order to accu-
rately time each delay.
Programming In-System
Flash memories can be programmed in-system or in a
standard PROM programmer. The device may be sol-
dered to the circuit board upon receipt of shipment and
programmed in-system. Alternatively, the device may
initially be programmed in a PROM programmer prior
to soldering the device to the board.
Am28F256
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AMD [ AMD ]
