B
A
C
D
E
F
G
Section
Addresses
CE
#
OE
#
#
WE
Data
Out
Data
In
20h
Data
A0h
V
CC
V
PP
11559G-9
G
A
B
C
D
E
F
Bus Cycle
Write
Write
Time-out
Write
Time-out
Read
Standby
Program
Address,
Program Data
C0h
(Stops
Program)
Compare
Data
Command
40h
N/A
N/A
N/A
Program
Command
Latch
Address and
Data
Proceed per
Programming
Algorithm
Program
Setup
Program
(10 µs)
Program
Verify
Transition
(6 µs)
Program
Verification
Function
Figure 4. AC Waveforms for Programming Operations
ANALYSIS OF PROGRAM TIMING WAVEFORMS
Program Setup/Program
Time-Out
Two-cycle write commands are required for program
operations (section A and B). The first program com-
mand (40h) is a Setup command and does not affect
the array data (section A).The second program com-
mand latches address and data required for program-
ming on the falling and rising edge of WE# respectively
(section B). The rising edge of this WE# pulse (section
B) also initiates the programming pulse. The device is
programmed on a byte by byte basis either sequentially
or randomly.
A software timing routine (10 µs duration) must be initi-
ated on the rising edge of the WE# pulse of section B.
Note: An integrated stop timer prevents any possibility
of overprogramming by limiting each time-out period of
10 µs.
Program-Verify
Upon completion of the program timing routine, the mi-
croprocessor must write the program-verify command
(C0h). This command terminates the programming op-
eration on the rising edge of the WE# pulse (section D).
The program-verify command also stages the device
for data verification (section F). Another software timing
routine (6 µs duration) must be executed to allow for
The program pulse occurs in section C.
18
Am28F256
AMD [ AMD ]
