A
B
C
D
E
F
G
Section
Addresses
CE
#
OE
#
#
WE
Data
Out
A0h
20h
Data
20h
V
CC
V
PP
11559G-7
G
A
B
C
D
E
F
Bus Cycle
Write
Write
Time-out
N/A
Write
A0h
Time-out
N/A
Read
Standby
Compare
Data
Command
Function
20h
20h
N/A
Proceed per
Erase
Algorithm
Erase
Setup
Erase
(10 ms)
Erase-
Verify
Transition
(6 µs)
Erase
Verification
Erase
Figure 2. AC Waveforms For Erase Operations
ANALYSIS OF ERASE TIMING WAVEFORM
Note: This analysis does not include the requirement
to program the entire array to 00h data prior to erasure.
Refer to the Flashrite Programming algorithm.
Time-Out
A software timing routine (10 ms duration) must be ini-
tiated on the rising edge of the WE# pulse of section B.
Erase Setup/Erase
Note: An integrated stop timer prevents any possibil-
ity of overerasure by limiting each time-out period of
10 ms.
This analysis illustrates the use of two-cycle erase
commands (section A and B). The first erase com-
mand (20h) is a Setup command and does not affect
the array data (section A). The second erase com-
mand (20h) initiates the erase operation (section B)
on the rising edge of this WE# pulse. All bytes of the
memory array are erased in parallel. No address infor-
mation is required.
Erase-Verify
Upon completion of the erase software timing routine,
the microprocessor must write the Erase-verify com-
mand (A0h). This command terminates the erase oper-
ation on the rising edge of the WE# pulse (section D).
The Erase-verify command also stages the device for
data verification (section F).
The erase pulse occurs in section C.
After each erase operation each byte must be verified.
The byte address to be verified must be supplied with
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