P R E L I M I N A R Y
SWITCHING CHARACTERISTICS over COMMERCIAL operating range
Read Cycle (33 MHz and 40 MHz)
Preliminary
Parameter
Description
General Timing Requirements
33 MHz
Min
40 MHz
Min
No. Symbol
Max
Max Unit
1
2
tDVCL Data in Setup
tCLDX Data in Hold(c)
8
3
5
2
ns
ns
General Timing Responses
3
4
5
6
7
8
9
tCHSV Status Active Delay
0
0
0
0
0
0
15
15
15
25
15
0
0
0
0
0
0
12
12
12
20
12
ns
ns
ns
ns
ns
ns
ns
tCLSH Status Inactive Delay
tCLAV AD Address Valid Delay and BHE
tCLAX Address Hold
tCLDV Data Valid Delay
tCHDX Status Hold Time
tCHLH ALE Active Delay
15
15
12
12
tCLCL–5
=20
10
tLHLL
ALE Width
tCLCL–10=20
ns
11
12
tCHLL
tAVLL
ALE Inactive Delay
AD Address Valid to ALE Low(a)
ns
ns
tCLCH –2
tCHCL–2
tCLCH –2
tCHCL –2
AD Address Hold from ALE
Inactive(a)
13
tLLAX
ns
14
15
16
tAVCH AD Address Valid to Clock High
tCLAZ AD Address Float Delay
tCLCSV MCS/PCS Active Delay
0
tCLAX=0
0
0
tCLAX=0
0
ns
ns
ns
15
15
12
12
MCS/PCS Hold from Command
17
tCXCSX
tCLCH–2
tCLCH–2
ns
Inactive(a)
18
19
20
21
22
23
tCHCSX MCS/PCS Inactive Delay
tDXDL DEN Inactive to DT/R Low(a)
tCVCTV Control Active Delay 1(b)
tCVDEX DEN Inactive Delay
0
0
15
0
0
12
ns
ns
ns
ns
ns
ns
0
15
15
15
0
12
12
12
0
0
tCHCTV Control Active Delay 2(b)
0
0
tLHAV ALE High to Address Valid
10
7.5
Read Cycle Timing Responses
24
25
26
27
28
tAZRL
tCLRL
AD Address Float to RD Active
RD Active Delay
0
0
ns
ns
ns
ns
ns
0
2tCLCL–15=45
0
15
15
0
2tCLCL–10=40
0
10
12
tRLRH RD Pulse Width
tCLRH RD Inactive Delay
tRHLH RD Inactive to ALE High(a)
tCLCH–3
tCLCH–2
RD Inactive to AD Address
tCLCL–5
=20
29
tRHAV
tCLCL–10=20
ns
Active(a)
59
66
67
68
tRHDX RD High to Data Hold on AD Bus(c)
tAVRL A Address Valid to RD Low(a)
0
0
ns
ns
ns
ns
2tCLCL–15=45
2tCLCL–10=40
tCHCSV CLKOUTA High to LCS/UCS Valid
tCHAV CLKOUTA High to A Address Valid
0
0
15
15
0
0
10
10
Notes:
All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions
are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC – 0.5 V.
a
b
c
Equal loading on referenced pins.
This parameter applies to the DEN, INTA1–INTA0, WR, WHB, and WLB signals.
If either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly.
64
Am186/188EM and Am186/188EMLV Microcontrollers
AMD [ AMD ]
