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AM188EMLV-33KC/W 参数 Datasheet PDF下载

AM188EMLV-33KC/W图片预览
型号: AM188EMLV-33KC/W
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能, 80C186- / 80C188兼容和80L186- / 80L188兼容的16位嵌入式微控制器 [High Performance, 80C186-/80C188-Compatible and 80L186-/80L188-Compatible, 16-Bit Embedded Microcontrollers]
分类和应用: 微控制器
文件页数/大小: 98 页 / 1582 K
品牌: AMD [ AMD ]
 浏览型号AM188EMLV-33KC/W的Datasheet PDF文件第62页浏览型号AM188EMLV-33KC/W的Datasheet PDF文件第63页浏览型号AM188EMLV-33KC/W的Datasheet PDF文件第64页浏览型号AM188EMLV-33KC/W的Datasheet PDF文件第65页浏览型号AM188EMLV-33KC/W的Datasheet PDF文件第67页浏览型号AM188EMLV-33KC/W的Datasheet PDF文件第68页浏览型号AM188EMLV-33KC/W的Datasheet PDF文件第69页浏览型号AM188EMLV-33KC/W的Datasheet PDF文件第70页  
P R E L I M I N A R Y  
SWITCHING CHARACTERISTICS over COMMERCIAL operating range  
Write Cycle (20 MHz and 25 MHz)  
Preliminary  
Parameter  
20 MHz  
Min  
25 MHz  
Min Max Unit  
No. Symbol  
General Timing Responses  
Description  
Max  
3
4
5
6
7
8
9
tCHSV Status Active Delay  
0
0
0
0
0
0
25  
25  
25  
25  
25  
0
0
0
0
0
0
20  
20  
20  
20  
20  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tCLSH Status Inactive Delay  
tCLAV AD Address Valid Delay and BHE  
tCLAX Address Hold  
tCLDV Data Valid Delay  
tCHDX Status Hold Time  
tCHLH ALE Active Delay  
25  
25  
20  
20  
tCLCL–10=  
40  
tCLCL–10=  
30  
10  
tLHLL  
ALE Width  
ns  
11  
12  
tCHLL  
tAVLL  
ALE Inactive Delay  
AD Address Valid to ALE Low(a)  
ns  
ns  
tCLCH  
tCHCL  
tCLCH  
tCHCL  
AD Address Hold from ALE  
Inactive(a)  
13  
tLLAX  
ns  
14  
16  
tAVCH AD Address Valid to Clock High  
tCLCSV MCS/PCS Active Delay  
0
0
0
0
ns  
ns  
25  
25  
20  
20  
MCS/PCS Hold from Command  
17  
tCXCSX  
tCLCH  
tCLCH  
ns  
Inactive(a)  
18  
19  
20  
22  
23  
tCHCSX MCS/PCS Inactive Delay  
tDXDL DEN Inactive to DT/R Low(a)  
tCVCTV Control Active Delay 1(b)  
tCHCTV Control Active Delay 2  
tLHAV ALE High to Address Valid  
0
0
0
0
ns  
ns  
ns  
ns  
ns  
0
25  
25  
0
20  
20  
0
0
20  
15  
Write Cycle Timing Responses  
30  
31  
tCLDOX Data Hold Time  
tCVCTX Control Inactive Delay(b)  
0
0
0
0
ns  
ns  
25  
20  
2tCLCL–10  
=90  
2tCLCL–10  
=70  
32  
33  
34  
35  
65  
67  
68  
tWLWH WR Pulse Width  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tWHLH WR Inactive to ALE High(a)  
tWHDX Data Hold after WR(a)  
tCLCH–2  
tCLCH–2  
tCLCL–10=  
40  
tCLCL–10=  
30  
tWHDEX WR Inactive to DEN Inactive(a)  
tAVWL A Address Valid to WR Low  
tCHCSV CLKOUTA High to LCS/UCS Valid  
tCLCH–3  
tCLCH–3  
tCLCL+tCHCL  
–3  
tCLCL+tCHCL  
–3  
0
25  
25  
25  
0
20  
20  
20  
CLKOUTA High to A Address  
tCHAV  
Valid  
0
0
87  
tAVBL  
A Address Valid to WHB, WLB Low  
tCHCL–3  
tCHCL–3  
Notes:  
All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions  
are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC – 0.5 V.  
a
b
Equal loading on referenced pins.  
This parameter applies to the DEN, INTA1–INTA0, WR, WHB, and WLB signals.  
66  
Am186/188EM and Am186/188EMLV Microcontrollers  
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