P R E L I M I N A R Y
COMMERCIAL SWITCHING CHARACTERISTICS AND WAVEFORMS
In the switching waveforms that follow, several abbre-
viations are used to indicate the specific periods of a
bus cycle. These periods are referred to as time states.
A typical bus cycle is composed of four consecutive
time states: t1, t2, t3, and t4. Wait states, which represent
multiple t3 states, are referred to as tw states. When no bus
cycle is pending, an idle (ti) state occurs.
In the switching parameter descriptions, the multi-
plexed address is referred to as the AD address bus; the
demultiplexed address is referred to as the A address
bus.
Key to Switching Waveforms
WAVEFORM
INPUT
OUTPUT
Must be
Steady
Will be
Steady
May
Will be
Change
Changing
from H to L
from H to L
May
Will be
Change
from L to H
Changing
from L to H
Don’t Care,
Any Change
Permitted
Changing,
State
Unknown
Does Not
Apply
Center
Line is High-
Impedance
Off State
Invalid
Invalid
60
Am186/188EM and Am186/188EMLV Microcontrollers
AMD [ AMD ]
