P R E L I M I N A R Y
Alphabetical Key to Switching Parameter Symbols
Parameter
Symbol
Parameter
Symbol
No.
Description
No.
Description
tARYCH
tARYCHL
tARYLCL
tAVBL
49 ARDY Resolution Transition Setup Time
51 ARDY Inactive Holding Time
52 ARDY Setup Time
tCLDX
tCLEV
tCLHAV
tCLRF
tCLRH
tCLRL
2
Data in Hold
71 CLKOUTA Low to SDEN Valid
62 HLDA Valid Delay
87 A Address Valid to WHB, WLB Low
14 AD Address Valid to Clock High
12 AD Address Valid to ALE Low
66 A Address Valid to RD Low
65 A Address Valid to WR Low
24 AD Address Float to RD Active
45 CLKOUTA Rise Time
82 CLKOUTA High to RFSH Invalid
27 RD Inactive Delay
tAVCH
tAVLL
25 RD Active Delay
tAVRL
tCLSH
tCLSL
4
Status Inactive Delay
tAVWL
tAZRL
72 CLKOUTA Low to SCLK Low
48 SRDY Transition Hold Time
55 Timer Output Delay
tCLSRY
tCLTMV
tCOAOB
tCVCTV
tCVCTX
tCVDEX
tCXCSX
tDVCL
tDVSH
tDXDL
tHVCL
tINVCH
tINVCL
tLCRF
tCH1CH2
tCHAV
tCHCK
tCHCL
tCHCSV
tCHCSX
tCHCTV
tCHCV
tCHCZ
tCHDX
tCHLH
tCHLL
68 CLKOUTA High to A Address Valid
38 X1 High Time
83 CLKOUTA to CLKOUTB Skew
20 Control Active Delay 1
44 CLKOUTA High Time
31 Control Inactive Delay
67 CLKOUTA High to LCS/UCS Valid
18 MCS/PCS Inactive Delay
21 DEN Inactive Delay
17 MCS/PCS Hold from Command Inactive
22 Control Active Delay 2
1
Data in Setup
64 Command Lines Valid Delay (after Float)
63 Command Lines Float Delay
75 Data Valid to SCLK High
19 DEN Inactive to DT/R Low
58 HOLD Setup
8
9
Status Hold Time
ALE Active Delay
53 Peripheral Setup Time
54 DRQ Setup Time
11 ALE Inactive Delay
tCHRFD
tCHSV
tCICOA
tCICOB
tCKHL
79 CLKOUTA High to RFSH valid
86 LCS Inactive to RFSH Active Delay
23 ALE High to Address Valid
10 ALE Width
3
Status Active Delay
tLHAV
69 X1 to CLKOUTA Skew
70 X1 to CLKOUTB Skew
39 X1 Fall Time
tLHLL
tLLAX
13 AD Address Hold from ALE Inactive
61 Maximum PLL Lock Time
84 LCS Precharge Pulse Width
57 RES Setup Time
tLOCK
tLRLL
tCKIN
36 X1 Period
tCKLH
40 X1 Rise Time
tRESIN
tRFCY
tRHAV
tRHDX
tRHLH
tRLRH
tSHDX
tSLDV
tCL2CL1
tCLARX
tCLAV
46 CLKOUTA Fall Time
50 ARDY Active Hold Time
85 RFSH Cycle Time
29 RD Inactive to AD Address Active
59 RD High to Data Hold on AD Bus
28 RD Inactive to ALE High
26 RD Pulse Width
5
6
AD Address Valid Delay
Address Hold
tCLAX
tCLAZ
15 AD Address Float Delay
43 CLKOUTA Low Time
37 X1 Low Time
tCLCH
tCLCK
77 SCLK High to SPI Data Hold
78 SCLK Low to SPI Data Valid
47 SRDY Transition Setup Time
35 WR Inactive to DEN Inactive
34 Data Hold after WR
tCLCL
42 CLKOUTA Period
80 LCS Inactive Delay
81 LCS Active Delay
16 MCS/PCS Active Delay
30 Data Hold Time
tSRYCL
tWHDEX
tWHDX
tWHLH
tWLWH
tCLCLX
tCLCSL
tCLCSV
tCLDOX
tCLDV
33 WR Inactive to ALE High
32 WR Pulse Width
7
Data Valid Delay
Note:
The following parameters are not defined or used as this time: 41, 56, 60, 73, 74, 76.
Am186/188EM and Am186/188EMLV Microcontrollers
61
AMD [ AMD ]
