P R E L I M I N A R Y
Numerical Key to Switching Parameter Symbols
Parameter
Number Symbol
Parameter
Symbol
Description
Data in Setup
Number
43
Description
CLKOUTA Low Time
1
2
tDVCL
tCLDX
tCHSV
tCLSH
tCLAV
tCLAX
tCLDV
tCHDX
tCHLH
tLHLL
tCHLL
tAVLL
tCLCH
tCHCL
Data in Hold
44
CLKOUTA High Time
3
Status Active Delay
Status Inactive Delay
AD Address Valid Delay
Address Hold
45
tCH1CH2
tCL2CL1
tSRYCL
tCLSRY
tARYCH
tCLARX
tARYCHL
tARYLCL
tINVCH
CLKOUTA Rise Time
4
46
CLKOUTA Fall Time
5
47
SRDY Transition Setup Time
SRDY Transition Hold Time
ARDY Resolution Transition Setup Time
ARDY Active Hold Time
ARDY Inactive Holding Time
ARDY Setup Time
6
48
7
Data Valid Delay
Status Hold Time
ALE Active Delay
ALE Width
49
8
50
9
51
10
11
12
52
ALE Inactive Delay
AD Address Valid to ALE Low
53
Peripheral Setup Time
DRQ Setup Time
54
tINVCL
AD Address Hold from ALE
Inactive
13
tLLAX
55
tCLTMV
Timer Output Delay
14
15
16
tAVCH
tCLAZ
AD Address Valid to Clock High
AD Address Float Delay
MCS/PCS Active Delay
57
58
59
tRESIN
tHVCL
tRHDX
RES Setup Time
HOLD Setup
tCLCSV
RD High to Data Hold on AD Bus
MCS/PCS Hold from Command
Inactive
17
tCXCSX
61
tLOCK
Maximum PLL Lock Time
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
42
tCHCSX
tDXDL
tCVCTV
tCVDEX
tCHCTV
tLHAV
MCS/PCS Inactive Delay
DEN Inactive to DT/R Low
Control Active Delay 1
DEN Inactive Delay
Control Active Delay 2
ALE High to Address Valid
AD Address Float to RD Active
RD Active Delay
62
63
64
65
66
67
68
69
70
71
72
75
77
78
79
80
81
82
83
84
85
86
87
tCLHAV
tCHCZ
tCHCV
tAVWL
tAVRL
tCHCSV
tCHAV
tCICOA
tCICOB
tCLEV
tCLSL
HLDA Valid Delay
Command Lines Float Delay
Command Lines Valid Delay (after Float)
A Address Valid to WR Low
A Address Valid to RD Low
CLKOUTA High to LCS/UCS Valid
CLKOUTA High to Address Valid
X1 to CLKOUTA Skew
tAZRL
tCLRL
tRLRH
tCLRH
tRHLH
tRHAV
tCLDOX
tCVCTX
tWLWH
tWHLH
tWHDX
tWHDEX
tCKIN
RD Pulse Width
X1 to CLKOUTB Skew
RD Inactive Delay
CLKOUTA Low to SDEN Valid
CLKOUTA Low to SCLK Low
Data Valid to SCLK High
RD Inactive to ALE High
RD Inactive to AD address Active
Data Hold Time
tDVSH
tSHDX
tSLDV
SCLK High to SPI Data Hold
SCLK Low to SPI Data Valid
CLKOUTA High to RFSH Valid
LCS Inactive Delay
Control Inactive Delay
WR Pulse Width
tCHRFD
tCLCLX
tCLCSL
tCLRF
tCOAOB
tLRLL
WR Inactive to ALE High
Data Hold after WR
WR Inactive to DEN Inactive
X1 Period
LCS Active Delay
CLKOUTA High to RFSH Invalid
CLKOUTA to CLKOUTB Skew
LCS Precharge Pulse Width
RFSH Cycle Time
tCLCK
tCHCK
tCKHL
tCKLH
tCLCL
X1 Low Time
X1 High Time
tRFCY
tLCRF
X1 Fall Time
LCS Inactive to RFSH Active Delay
A Address Valid to WHB, WLB Low
X1 Rise Time
tAVBL
CLKOUTA Period
Note:
The following parameters are not defined or used at this time: 41, 56, 60, 73, 74, and 76.
62
Am186/188EM and Am186/188EMLV Microcontrollers
AMD [ AMD ]
