P R E L I M I N A R Y
Offset
(Hexadecimal)
Register Name
w
w
PIO Data 1 Register
7A
78
76
74
72
70
PIO Direction 1 Register
PIO Mode 1 Register
PIO Data 0 Register
PIO Direction 0 Register
PIO Mode 0 Register
w
w
Timer 2 Mode/Control Register
66
62
60
5E
5C
Timer 2 Maxcount Compare A Register
Timer 2 Count Register
Timer 1 Mode/Control Register
Timer 1 Maxcount Compare B Register
Timer 1 Maxcount Compare A Register
Timer 1 Count Register
5A
58
Timer 0 Mode/Control Register
Timer 0 Maxcount Compare B Register
Timer 0 Maxcount Compare A Register
Timer 0 Count Register
56
54
52
50
w
w
Serial Port Interrupt Control Register
Watchdog Timer Control Register
INT4 Control Register
44
42
40
INT3 Control Register
3E
3C
3A
38
36
34
32
30
2E
2C
2A
INT2 Control Register
INT1 Control Register
INT0 Control Register
DMA 1 Interrupt Control Register
DMA 0 Interrupt Control Register
Timer Interrupt Control Register
Interrupt Status Register
Interrupt Request Register
In-service Register
Priority Mask Register
Interrupt Mask Register
Poll Status Register
28
26
24
22
20
18
16
14
12
10
Poll Register
End-of-Interrupt Register
Interrupt Vector Register
Synchronous Serial Receive Register
Synchronous Serial Transmit 0 Register
Synchronous Serial Transmit 1 Register
Synchronous Serial Enable Register
Synchronous Serial Status Register
Changed from 80C186
microcontroller.
Note: Gaps in offset addresses indicate
reserved registers.
Figure 7. Peripheral Control Block Register Map (continued)
Am186/188EM and Am186/188EMLV Microcontrollers
40
AMD [ AMD ]
