P R E L I M I N A R Y
Pseudo Static RAM (PSRAM) Support
PERIPHERAL CONTROL BLOCK (PCB)
The Am186EM and Am188EM microcontrollers sup-
port the use of PSRAM devices in low memory chip-se-
lect (LCS) space only. When PSRAM mode is enabled,
the timing for the LCS signal is modified by the chip-select
control unit to provide a CS precharge period during
PSRAM accesses. The 40-MHz timing of the Am186EM
and Am188EM microcontrollers is appropriate to allow
70-ns PSRAM to run with one wait state. PSRAM mode is
enabled through a bit in the Low Memory Chip-Select
(LMCS) Register. The PSRAM feature is disabled on CPU
reset.
The integrated peripherals of the Am186EM and
Am188EM microcontrollers are controlled by 16-bit
read/write registers. The peripheral registers are con-
tained within an internal 256-byte control block. The
registers are physically located in the peripheral de-
vices they control, but they are addressed as a single
256-byte block. Figure 7 shows a map of these regis-
ters.
Reading and Writing the PCB
Code that is intended to execute on the Am188EM mi-
crocontroller should perform all writes to the PCB reg-
isters as byte writes. These writes will transfer 16 bits
of data to the PCB register even if an 8-bit register is
named in the instruction. For example, out dx, alre-
sults in the value of axbeing written to the port address in
dx. Reads to the PCB should be done as word reads.
Code written in this manner will run correctly on the
Am188EM microcontroller and on the Am186EM micro-
controller.
In addition to the LCS timing changes for PSRAM pre-
charge, the PSRAM devices also require periodic refresh of
all internal row addresses to retain their data. Although re-
fresh of PSRAM can be accomplished several ways, the
Am186EM and Am188EM microcontrollers implement auto
refresh only.
The Am186EM and Am188EM microcontrollers gener-
ate RFSH, a refresh signal, to the PSRAM devices when
PSRAM mode is enabled. No refresh address is required
by the PSRAM when using the auto refresh mechanism.
The RFSH signal is multiplexed with the MCS3 signal pin.
When PSRAM mode is enabled, MCS3 is not available for
use as a chip-select signal.
Unaligned reads and writes to the PCB result in unpre-
dictable behavior on both the Am186EM and
Am188EM microcontrollers.
For a complete description of all the registers in the
PCB, see the Am186EM and Am188EM Microcontrol-
lers User’s Manual, order# 19713.
The refresh control unit must be programmed before
accessing PSRAM in LCS space. The refresh counter
in the Clock Prescaler (CDRAM) Register must be con-
figured with the required refresh interval value. The
ending address of LCS space and the ready and wait-
state generation in the LMCS Register must also be
programmed. The refresh counter reload value in the
CDRAM Register should not be set to less than 18
(12h) in order to provide time for processor cycles
within refresh. The refresh address counter must be set
to 000000h to prevent another chip select from assert-
ing.
LCS is held High during a refresh cycle. The A bus is
not used during refresh cycles. The LMCS Register
must be configured to external ready ignored (R2=1)
with one wait state (R1–R0=01b), and the PSRAM
mode enable bit (SE) must be set.
38
Am186/188EM and Am186/188EMLV Microcontrollers
AMD [ AMD ]
