P R E L I M I N A R Y
Offset
(Hexadecimal)
Register Name
FE
Peripheral Control Block Relocation Register
w
w
w
w
Reset Configuration Register
F6
F4
Processor Release Level Register
F0
PDCON Register
E4
E2
E0
Enable RCU Register
Clock Prescaler Register
Memory Partition Register
w
w
DA
D8
D6
D4
D2
D0
CA
DMA 1 Control Register
DMA 1 Transfer Count Register
DMA 1 Destination Address High Register
DMA 1 Destination Address Low Register
DMA 1 Source Address High Register
DMA 1 Source Address Low Register
DMA 0 Control Register
DMA 0 Transfer Count Register
C8
C6
C4
C2
C0
DMA 0 Destination Address High Register
DMA 0 Destination Address Low Register
DMA 0 Source Address High Register
DMA 0 Source Address Low Register
w
w
PCS and MCS Auxiliary Register
Midrange Memory Chip Select Register
Peripheral Chip Select Register
A8
A6
A4
A2
Low Memory Chip Select Register
A0
Upper Memory Chip Select Register
w
w
88
86
84
82
80
Serial Port Baud Rate Divisor Register
Serial Port Receive Register
Serial Port Transmit Register
Serial Port Status Register
Changed from 80C186
microcontroller.
Note: Gaps in offset addresses indicate
Serial Port Control Register
reserved registers.
Figure 7. Peripheral Control Block Register Map
Am186/188EM and Am186/188EMLV Microcontrollers
39
AMD [ AMD ]
