P R E L I M I N A R Y
t1
t2
t3
t4
Address
Phase
Data
Phase
CLKOUTA
A19–A0
Address
AD7–AD0
(Read)
Data
AO15–AO8
Address
Data
AD7–AD0
(Write)
LCS, UCS
Figure 6. Am188EM Microcontroller—Read and Write with Address Bus Disable In Effect
BUS INTERFACE UNIT
Byte Write Enables
The bus interface unit controls all accesses to external
peripherals and memory devices. External accesses
include those to memory devices, as well as those to
memory-mapped and I/O-mapped peripherals and the
peripheral control block. The Am186EM and
Am188EM microcontrollers provide an enhanced bus
interface unit with the following features:
The Am186EM microcontroller provides the WHB
(Write High Byte) and WLB (Write Low Byte) signals, which
act as byte write enables.
WHB is the logical OR of BHE and WR. WHB is Low
when BHE and WR are both Low. WLB is the logical
OR of AD0 and WR. WLB is Low when AD0 and WR
are both Low. WB is Low whenever a byte is written on
the Am188EM microcontroller.
n A nonmultiplexed address bus
n Separate byte write enables for high and low bytes
The byte write enables are driven in conjunction with
the nonmultiplexed address bus as required for the
write timing requirements of common SRAMs.
in the Am186EM microcontroller only
n Pseudo Static RAM (PSRAM) support
The standard 80C186/188 multiplexed address and
data bus requires system interface logic and an exter-
nal address latch. On the Am186EM and Am188EM
microcontrollers, new byte write enables, PSRAM con-
trol logic, and a new nonmultiplexed address bus can
reduce design costs by eliminating this external logic.
Nonmultiplexed Address Bus
The nonmultiplexed address bus (A19–A0) is valid
one-half CLKOUTA cycle in advance of the address on
the AD bus. When used in conjunction with the modi-
fied UCS and LCS outputs and the byte write enable sig-
nals, the A19–A0 bus provides a seamless interface to
SRAM, PSRAM, and Flash/EPROM memory systems.
Am186/188EM and Am186/188EMLV Microcontrollers
37
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