P R E L I M I N A R Y
SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges
Clock (20 MHz and 25 MHz)
Preliminary
Parameter
Description
20 MHz
Min
25 MHz
Min
No.
Symbol
Max
Max
Unit
CLKIN Requirements
36
37
38
39
40
tCKIN
tCLCK
tCHCK
tCKHL
tCKLH
X1 Period(a)
X1 Low Time (1.5 V)(a)
X1 High Time (1.5 V)(a)
X1 Fall Time (3.5 to 1.0 V)(a)
X1 Rise Time (1.0 to 3.5 V)(a)
50
15
15
60
40
15
15
60
ns
ns
ns
ns
ns
5
5
5
5
CLKOUT Timing
42
43
44
45
tCLCL
tCLCH
tCHCL
CLKOUTA Period
50
40
ns
ns
ns
ns
CLKOUTA Low Time (CL=50 pF)
CLKOUTA High Time (CL=50 pF)
0.5tCLCL–2=23
0.5tCLCL–2=23
0.5tCLCL–2=18
0.5tCLCL–2=18
tCH1CH2 CLKOUTA Rise Time
(1.0 to 3.5 V)
3
3
3
3
46
tCL2CL1
CLKOUTA Fall Time
(3.5 to 1.0 V)
ns
61
69
70
tLOCK
tCICOA
tCICOB
Maximum PLL Lock Time
X1 to CLKOUTA Skew
X1 to CLKOUTB Skew
1
1
ms
ns
ns
15
25
15
25
Notes:
All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions
are with CL =50 pF. For switching tests, VIL=0.45 V and VIH =2.4 V, except at X1 where VIH =VCC – 0.5 V.
a
The specifications for CLKIN are applicable to the normal PLL and CLKDIV2 modes.
The PLL should be used for operations from 16.667 MHz to 40 MHz. For operations below 16.667 MHz, the CLKDIV2
mode should be used.
Because the CLKDIV2 input frequency is two times the system frequency, the specifications for twice the frequency should
be used for CLKDIV2 mode. For example, use the 20 MHz CLKIN specifications for 10 MHz operation.
Am186ED/EDLV Microcontrollers
79
AMD [ AMD ]
