P R E L I M I N A R Y
SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges
Software Halt Cycle (20 MHz and 25 MHz)
Preliminary
Parameter
Description
20 MHz
Min
25 MHz
Min
No.
Symbol
Max
Max
Unit
General Timing Responses
3
4
tCHSV
tCLSH
tCLAV
tCHLH
tLHLL
Status Active Delay
0
0
0
25
25
25
25
0
0
0
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
Status Inactive Delay
5
AD Address Invalid Delay and BHE
ALE Active Delay
9
10
11
19
22
68
ALE Width
tCLCL–10=40
tCLCL–10=30
tCHLL
tDXDL
tCHCTV
tCHAV
ALE Inactive Delay
25
20
DEN Inactive to DT/R Low(a)
Control Active Delay 2(b)
CLKOUTA High to A Address Invalid
0
0
0
0
0
0
25
25
20
20
Notes:
All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions
are with CL =50 pF. For switching tests, VIL=0.45 V and VIH =2.4 V, except at X1 where VIH =VCC – 0.5 V.
a
b
Testing is performed with equal loading on referenced pins.
This parameter applies to the DEN signal.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges
Software Halt Cycle (33 MHz and 40 MHz)
Preliminary
Parameter
Description
33 MHz
Min
40 MHz
Min
No.
Symbol
Max
Max
Unit
General Timing Responses
3
4
tCHSV
tCLSH
tCLAV
tCHLH
tLHLL
Status Active Delay
0
0
0
15
15
15
15
0
0
0
12
12
12
12
ns
ns
ns
ns
ns
ns
ns
ns
ns
Status Inactive Delay
5
AD Address Invalid Delay and BHE
ALE Active Delay
9
10
11
19
22
68
ALE Width
tCLCL–10=20
tCLCL–5=20
tCHLL
tDXDL
tCHCTV
tCHAV
ALE Inactive Delay
15
12
DEN Inactive to DT/R Low(a)
Control Active Delay 2(b)
CLKOUTA High to A Address Invalid
0
0
0
0
0
0
15
15
12
10
Notes:
All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions
are with CL =50 pF. For switching tests, VIL=0.45 V and VIH =2.4 V, except at X1 where VIH =VCC – 0.5 V.
a
b
Testing is performed with equal loading on referenced pins.
This parameter applies to the DEN signal.
Am186ED/EDLV Microcontrollers
77
AMD [ AMD ]
