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AM186EDLV-20KC/W 参数 Datasheet PDF下载

AM186EDLV-20KC/W图片预览
型号: AM186EDLV-20KC/W
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能, 80C186-和80C188兼容的16位嵌入式微控制器 [High Performance, 80C186- and 80C188-Compatible, 16-Bit Embedded Microcontrollers]
分类和应用: 微控制器
文件页数/大小: 88 页 / 1493 K
品牌: AMD [ AMD ]
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P R E L I M I N A R Y  
SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges  
Ready and Peripheral (20 MHz and 25 MHz)  
Preliminary  
20 MHz  
Preliminary  
25 MHz  
Parameter  
Description  
Ready and Peripheral Timing Requirements  
No.  
Symbol  
Min  
Max  
Min  
Max  
Unit  
47  
48  
49  
50  
51  
52  
53  
54  
tSRYCL  
tCLSRY  
tARYCH  
tCLARX  
tARYCHL  
tARYLCL  
tINVCH  
SRDY Transition Setup Time(a)  
SRDY Transition Hold Time(a)  
ARDY Resolution Transition Setup Time(b)  
ARDY Active Hold Time(a)  
ARDY Inactive Holding Time  
ARDY Setup Time(a)  
10  
3
10  
3
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
10  
4
10  
4
6
6
15  
10  
10  
15  
10  
10  
Peripheral Setup Time(b)  
DRQ Setup Time(b)  
tINVCL  
Peripheral Timing Responses  
55  
tCLTMV  
Timer Output Delay  
25  
20  
ns  
Notes:  
All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions  
are with CL =50 pF. For switching tests, VIL=0.45 V and VIH =2.4 V, except at X1 where VIH =VCC – 0.5 V.  
a
b
This timing must be met to guarantee proper operation.  
This timing must be met to guarantee recognition at the clock edge.  
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges  
Ready and Peripheral (33 MHz and 40 MHz)  
Preliminary  
Parameter  
Description  
Ready and Peripheral Timing Requirements  
33 MHz  
Min  
40 MHz  
Min  
No.  
Symbol  
Max  
Max  
Unit  
47  
48  
49  
50  
51  
52  
53  
54  
tSRYCL  
tCLSRY  
tARYCH  
tCLARX  
tARYCHL  
tARYLCL  
tINVCH  
SRDY Transition Setup Time(a)  
SRDY Transition Hold Time(a)  
ARDY Resolution Transition Setup Time(b)  
ARDY Active Hold Time(a)  
ARDY Inactive Holding Time  
ARDY Setup Time(a)  
8
3
5
2
5
3
5
5
5
5
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
8
4
6
10  
8
Peripheral Setup Time(b)  
DRQ Setup Time(b)  
tINVCL  
8
Peripheral Timing Responses  
55  
tCLTMV  
Timer Output Delay  
15  
12  
ns  
Notes:  
All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions  
are with CL =50 pF. For switching tests, VIL=0.45 V and VIH =2.4 V, except at X1 where VIH =VCC – 0.5 V.  
a
b
This timing must be met to guarantee proper operation.  
This timing must be met to guarantee recognition at the clock edge.  
82  
Am186ED/EDLV Microcontrollers  
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