P R E L I M I N A R Y
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges
Interrupt Acknowledge Cycle (33 MHz and 40 MHz)
Preliminary
Parameter
Description
33 MHz
Min
40 MHz
Min
No.
Symbol
Max
Max
Unit
General Timing Requirements
1
2
tDVCL
tCLDX
Data in Setup
Data in Hold
8
3
5
2
ns
ns
General Timing Responses
3
tCHSV
tCLSH
tCLDV
tCHDX
tCHLH
tLHLL
Status Active Delay
0
0
0
0
15
15
15
0
0
0
0
12
12
12
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
Status Inactive Delay
Data Valid Delay
7
8
Status Hold Time
9
ALE Active Delay
15
15
15
12
12
12
10
11
12
15
19
20
21
22
23
31
68
ALE Width
tCLCL–10=20
tCLCL–5=20
tCHLL
tAVLL
ALE Inactive Delay
AD Address Invalid to ALE Low(a)
AD Address Float Delay
DEN Inactive to DT/R Low(a)
Control Active Delay 1(b)
DEN Inactive Delay
Control Active Delay 2(c)
ALE High to Address Valid
Control Inactive Delay(b)
CLKOUTA High to A Address Valid
tCLCH
tCLCH
tCLAZ
tDXDL
tCVCTV
tCVDEX
tCHCTV
tLHAV
tCLAX=0
tCLAX=0
0
0
0
0
15
15
15
12
12
12
0
0
0
0
10
0
7.5
0
tCVCTX
tCHAV
15
15
12
10
0
0
Notes:
All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions
are with CL =50 pF. For switching tests, VIL=0.45 V and VIH =2.4 V, except at X1 where VIH =VCC – 0.5 V.
a
b
c
Testing is performed with equal loading on referenced pins.
This parameter applies to the INTA1–INTA0 signals.
This parameter applies to the DEN and DT/R signals.
Am186ED/EDLV Microcontrollers
75
AMD [ AMD ]
