P R E L I M I N A R Y
INTERRUPT ACKNOWLEDGE CYCLE WAVEFORMS
t1
t2
t3
t4
tW
CLKOUTA
68
Address
A19–A0
7
8
Invalid
S6
S6
S6
1
(b)
2
12
15
AD15–AD0
Ptr
23
9
ALE
10
11
4
BHE
BHE
31
21
INTA1–INTA0
DEN
20
(c)
19
3
22
22
DT/R
(d)
(a)
4
22
Status
S2–S0
Notes:
a
The status bits become inactive in the state preceding t4.
b
The data hold time lasts only until the interrupt acknowledge signal deasserts, even if the interrupt acknowledge
transition occurs prior to tCLDX (min).
c
This parameter applies for an interrupt acknowledge cycle that follows a write cycle.
If followed by a write cycle, this change occurs in the state preceding that write cycle.
d
76
Am186ED/EDLV Microcontrollers