P R E L I M I N A R Y
DRAM Read Cycle Timing with No-Wait States
t3
t4
t1
t2
t3
t4
t1
CLKOUTA
AD[15:0]
A[17:1]
5
15
1
Addr.
Data
2
68
101
Column
Row
110
103
102
RAS
CAS
108
105
104
25
27
RD(a)
Note:
a
The RD output connects to the DRAM output enable (OE) pin for read operations.
DRAM Read Cycle Timing with Wait State(s)
t4
t1
t2
t3
tw
t4
t1
CLKOUTA
AD[15:0]
A[17:1]
5
15
1
Addr.
Data
2
68
101
Row
102
Column
110
107
RAS
CAS
109
105
27
104
25
RD(a)
Note:
a
The RD output connects to the DRAM output enable (OE) pin for read operations.
Am186ED/EDLV Microcontrollers
71