D A T A S H E E T
definitions). In addition, the following hardware data protec-
tion measures prevent accidental erasure or programming,
which might otherwise be caused by spurious system level
signals during VCC power-up and power-down transitions, or
from system noise.
START
RESET# = VID
(Note 1)
Low V
Write Inhibit
CC
When VCC is less than VLKO, the device does not accept any
write cycles. This protects data during VCC power-up and
power-down. The command register and all internal pro-
gram/erase circuits are disabled, and the device resets. Sub-
Perform Erase or
Program Operations
sequent writes are ignored until VCC is greater than VLKO
.
The system must provide the proper signals to the control
pins to prevent unintentional writes when VCC is greater than
RESET# = VIH
VLKO
.
Write Pulse “Glitch” Protection
Temporary Sector
Unprotect Completed
(Note 2)
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE#
do not initiate a write cycle.
Logical Inhibit
Notes:
Write cycles are inhibited by holding any one of OE# = VIL,
CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and
WE# must be a logical zero while OE# is a logical one.
1. All protected sectors unprotected.
2. All previously protected sectors are protected once again.
Power-Up Write Inhibit
Figure 2. Temporary Sector Unprotect Operation
If WE# = CE# = VIL and OE# = VIH during power up, the de-
vice does not accept commands on the rising edge of WE#.
The internal state machine is automatically reset to reading
array data on power-up.
Hardware Data Protection
The command sequence requirement of unlock cycles for
programming or erasing provides data protection against in-
advertent writes (refer to Table 5 on page 18 for command
14
Am29SL400C
Am29SL400C_00_A6 January 23, 2007
AMD [ AMD ]
