D A T A S H E E T
The device features an Unlock Bypass mode to facilitate
If the device is deselected during erasure or programming,
the device draws active current until the operation is com-
pleted.
faster programming. Once the device enters the Unlock By-
pass mode, only two write cycles are required to program a
word or byte, instead of four. The Word/Byte Program Com-
mand Sequence‚ on page 15 has details on programming
data to the device using both standard and Unlock Bypass
command sequences.
ICC3 in DC Characteristics‚ on page 24 represents the
standby current specification.
Automatic Sleep Mode
An erase operation can erase one sector, multiple sectors, or
the entire device. Table 2 on page 11 and Table 3 on
page 11 indicate the address space that each sector occu-
pies. A sector address consists of the address bits required
to uniquely select a sector. Command Definitions‚ on
page 18 has details on erasing a sector or the entire chip, or
suspending/resuming the erase operation.
The automatic sleep mode minimizes Flash device energy
consumption. The device automatically enables this mode
when addresses remain stable for tACC + 50 ns. The auto-
matic sleep mode is independent of the CE#, WE#, and OE#
control signals. Standard address access timings provide
new data when addresses are changed. While in sleep
mode, output data is latched and always available to the sys-
tem. ICC4 in the DC Characteristics table represents the au-
tomatic sleep mode current specification.
After the system writes the autoselect command sequence,
the device enters the autoselect mode. The system can then
read autoselect codes from the internal register (which is
separate from the memory array) on DQ7–DQ0. Standard
read cycle timings apply in this mode. Refer to Autoselect
Mode‚ on page 11 and Autoselect Command Sequence‚ on
page 15 for more information.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting
the device to reading array data. When the RESET# pin is
driven low for at least a period of tRP, the device immedi-
ately terminates any operation in progress, tristates all out-
put pins, and ignores all read/write commands for the
duration of the RESET# pulse. The device also resets the in-
ternal state machine to reading array data. The operation
that was interrupted should be reinitiated once the device is
ready to accept another command sequence, to ensure data
integrity.
ICC2 in the DC Characteristics table represents the active
current specification for the write mode. The AC Character-
istics‚ on page 28 contains timing specification tables and
timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status bits
on DQ7–DQ0. Standard read cycle timings and ICC read
specifications apply. Refer to Write Operation Status‚ on
page 19 for more information, and to AC Characteristics‚ on
page 28 for timing diagrams.
Current is reduced for the duration of the RESET# pulse.
When RESET# is held at VSS 0.2 V, the device draws
CMOS standby current (ICC4). If RESET# is held at VIL but
not within VSS 0.2 V, the standby current is greater.
The RESET# pin may be tied to the system reset circuitry. A
system reset would thus also reset the Flash memory, en-
abling the system to read the boot-up firmware from the
Flash memory.
Standby Mode
When the system is not reading or writing to the device, it
can place the device in the standby mode. In this mode, cur-
rent consumption is greatly reduced, and the outputs are
placed in the high impedance state, independent of the OE#
input.
If RESET# is asserted during a program or erase operation,
the RY/BY# pin remains a 0 (busy) until the internal reset op-
eration is complete, which requires a time of tREADY (during
Embedded Algorithms). The system can thus monitor
RY/BY# to determine whether the reset operation is com-
plete. If RESET# is asserted when a program or erase oper-
ation is not executing (RY/BY# pin is 1), the reset operation
is completed within a time of tREADY (not during Embedded
Algorithms). The system can read data tRH after the RE-
SET# pin returns to VIH.
The device enters the CMOS standby mode when the CE#
and RESET# pins are both held at VCC ± 0.2 V. (Note that
this is a more restricted voltage range than VIH.) If CE# and
RESET# are held at VIH, but not within VCC ± 0.2 V, the de-
vice will be in the standby mode, but the standby current will
be greater. The device requires standard access time (tCE
)
for read access when the device is in either of these standby
modes, before it is ready to read data.
Refer to the AC Characteristics tables for RESET# parame-
ters and to Figure 15‚ on page 29 for the timing diagram.
The device also enters the standby mode when the RESET#
pin is driven low. Refer to the next section, RESET#: Hard-
ware Reset Pin.
Output Disable Mode
When the OE# input is at VIH, output from the device is dis-
abled. The output pins are placed in the high impedance
state.
10
Am29SL400C
Am29SL400C_00_A6 January 23, 2007
AMD [ AMD ]
