Revision 1.02 – June 27, 2006
S5935 – PCI Product
Data Book
nv Memory Device Timing Requirements
Memory Device Requirements for Read Accesses
For serial nv memory devices, the serial clock output
frequency is the PCI clock frequency divided by 512.
This is approximately 65 KHz (with a 33 MHz PCI
clock). Any serial memory device that operates at this
frequency is compatible with the S5935.
Timing
Read cycle time
Spec.
8T(max)
7T–10(max)
T(max)
T = 30 ns
240 ns
200 ns
30 ns
Address valid to data valid
Address valid to read active
Read active to data valid
Read pulse width
For byte-wide accesses, the S5935 generates the
waveforms shown in Figures 5 and 6. Figure 5 shows
an nv memory read operation. Figure 6 shows an nv
memory write operation. Read operations are always
the same length. Write operations, due to the charac-
teristics of reprogrammable nv memory devices, may
be controlled through a programming sequence.
6T–10(max)
6T(max)
—
170 ns
180 ns
2 ns
Data hold from read inactive
Figure 68. nv Memory Read Operation
t
35
ERD#
t
37
(OUTPUT)
t
t
t
39
36
38
EA[15:0]
Address Valid
(OUTPUT)
t
t
41
40
EQ[7:0]
Data Valid
(INPUT)
124
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