Revision 1.02 – June 27, 2006
S5935 – PCI Product
Data Book
SELECT#, BE[3:0]#, and ADR[6:2]. RD# and WR#
must be deasserted when PTADR# is asserted, but
SELECT# may be asserted. These inputs automati-
cally drive the address (internally) to 28h and assert all
byte enables. The ADR[6:2] and BE[3:0]# are ignored
when using the PTADR# direct access input. When
PTADR# is asserted, the contents of the APTA register
are immediately driven onto the Add-On data bus.
The S5935 automatically performs the read and write
accesses when programmed for byte wide devices.
Accessing Non-Volatile Memory
The nv memory, if implemented, can be accessed
through the PCI interface or the Add-On interface.
Accesses from both the PCI side and the Add-On side
must be synchronous with the PCI clock (BPCLK for
the Add-On). Accesses to the nv memory from the PCI
interface are through the Bus Master Control/Status
Register (MCSR) PCI Operation Register.
The PTADR# direct access signal accesses the Pass-
Thru address register as 16-bits or 32-bits, whatever
the MODE pin is configured for. For 16-bit mode,
PTADR# only presents the lower 16-bits of the APTA
register.
Accesses to the nv memory from the Add-On interface
are through the Add-On General Control/Status Regis-
ter (AGCSTS) Add-On Operation Register. Accesses
to the MCSR register are from the PCI bus and are,
therefore, automatically synchronous to the PCI clock.
Accesses to the AGCSTS register from the Add-On
side must be synchronous with respect to BPCLK.
PTRDY# indicates that the Add-On has completed the
current Pass-Thru access. Multiple Add-On reads or
writes may occur to the Pass-Thru data (APTD) regis-
ter before asserting PTRDY#. This may be required for
8-bit or 16-bit Add-On interfaces using multiple
accesses to the 32-bit Pass-Thru data register. In
some cases, the Add-On bus may be 32-bits, but logic
may require multiple BPCLK periods to read or write
data. In this situation, accesses may be extended by
holding off PTRDY#. PTRDY# must be synchronized
to BPCLK.
Some nv memories may contain Expansion ROM
BIOS code for use by the host software. During initial-
ization, the Expansion BIOS is located within system
memory. The starting location of the nv memory is
stored in the Expansion ROM Base Address Register
in the S5935 PCI Configuration Registers. A PCI read
from this region results in the S5935 performing four
consecutive byte access to the nv memory device.
Writes to the nv memory are not allowed by writing to
this region. Writes to the nv memory must be per-
formed as described below.
NON-VOLATILE MEMORY INTERFACE
The S5935 allows read and write access to the nv
memory device used for configuration. Reads are nec-
essary during device initialization as configuration
information is downloaded into the S5935. If an expan-
sion BIOS is implemented in the nv memory, the host
transfers (shadows) the code into system DRAM.
Writes are useful for in-field updates to expansion
BIOS code. This allows software to update the nv
memory contents without altering hardware.
The S5935 contains two latches within the MCSR reg-
ister to control and access the NVRAM. One is an 8 bit
latch called the NVRAM Address/Data Register which
is used to hold NVRAM address and data information.
The other is a 3 bit latch called the NVRAM Access
Control Register which is used to direct the address
and data information and to control the NVRAM itself.
Reading or writing to the NVRAM is performed through
bits D31:29 of this register. These bits are enable and
decode controls rather than a command or instruction
to be executed. D31 of this register is the primary
enable bit which allows all accesses to occur. When
written to a ‘1’, D31 enables the decode bits D30 and
D29 to direct the data contained in the address/data
latch, D23:16, to the low address, high address or data
latches. D31 should be thought of as “opening a door”
where as long as D31 = 1, then the door is open for
address or data information to be altered. The table on
page 5-16 of the S5935 data book shows the D31:29
bit combinations for reading, writing, and loading ad-
dress/data information. Additionally, D31 doubles as
an S5935 status bit. A ‘1’ indicates that the S5935 is
currently busy reading or writing to the NVRAM. A ‘0’
indicates a complete or inactive state.
Non-Volatile Memory Interface Signals
For serial nv memory devices, there are only two sig-
nals used to interface with nv memory. SCL is the
serial clock, and SDA is the serial data line. The func-
tionality of these signals is described in-detail in the
PIN description Section of this book. The designer
does not need to generate the timings for SCL and
SDA. The S5935 automatically performs the correct
serial access when programmed for serial devices.
For byte-wide nv memory devices, there is an 8-bit
data bus (EQ7:0), and a 16-bit address bus (EA15:0)
dedicated for the nv memory interface. When a serial
nv memory is implemented, many of these pins have
alternate functions. The S5935 also has read (ERD#)
and write (EWR#) outputs to drive the OE# and WR#
inputs on a byte-wide nv memory. The designer does
not need to generate the timings for these outputs.
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