Revision 1.02 – June 27, 2006
S5935 – PCI Product
Data Book
For the examples below, we will assume the S5935 is
I/O mapped with a base address of FC00h. These
examples will read one byte of the Vendor ID and write
one byte to the Vendor ID.
This example will write 1 byte from NVRAM location 0040h and read it back:
In
FC00h + 3Fh (offset of NVRAM Access Control Register) until D31 = 0 (not busy).
Out
FC00h + 3FH an 80h (CMD to load the low address byte). This sets decode bits and opens door for low address
latch.
Out
Out
FC00h + 3Eh (offset of Address/Data Register) 40h (the low byte of the address desired) 40h goes into latch but is
not latched yet.
FC00h + 3Fh an A0h (CMD to load the high address byte). This latches the low address through changing the
decode bits and opens the door for the high address latch.
Out
Out
Out
Out
FC00h + 3Eh a 00h (the high byte of the address desired). 00h goes into the latch but is not latched yet.
FC00h + 3Fh an 00h (inactive CMD). This latches the high address through the disabling D31, ‘closes the door’.
FC00h + 3Eh DATA (the data byte to be written). DATA byte goes into the latch but is not latched yet.
FC00h + 3Fh a C0h (CMD to write the data byte). This latches the data byte through changing the decode bits and
begins to write NVRAM data operation.
In
FC00h + 3Fh until D31 = 0 (not busy).
FC00h + 3Fh an E0h (CMD to read the address latched).
FC00h + 3Fh until D31 = 0 (not busy).
FC00h + 3Eh the data.
Out
In
In
122
DS1527
AMCC Confidential and Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
