Revision 1.02 – June 27, 2006
S5935 – PCI Product
Data Book
This example will read 1 byte from NVRAM location 0040h:
In
FC00h + 3Fh (offset of NVRAM Access Control Register) until D31 = 0 (not busy).
Out
FC00h + 3Fh an 80h (CMD to load the low address byte). This sets decode bits and opens door for low address
latch.
Out
Out
FC00h + 3Eh (offset of Address/Data Register) 40h (the low byte of the address desired) 40h goes into latch but is
not latched yet.
FC00h + 3Fh an A0h (CMD to load the high address byte). This latches the low address through changing the
decode bits and opens the door for the high address latch.
Out
Out
FC00h + 3Eh a 00h (the high byte of the address desired) 00h goes into latch but is not latched yet.
FC00h + 3Fh an E0h (CMD to read NVRAM data). This latches the high address through changing the decode bits
and begins to read the NVRAM data operation.
In
In
FC00h + 3Fh until D31 = 0 (not busy).
FC00h + 3Eh the data.
This example will read 1 byte from NVRAM location 0041h and contains an extra step to demonstrate D31 operation:
In
FC00h + 3Fh (offset of NVRAM Access Control Register) until D31 = 0 (not busy).
Out
FC00h + 3Fh an 80h (CMD to load the low address byte). This sets decode bits and opens the door for low
address latch.
Out
Out
Out
FC00h + 3Eh (offset of Address/Data Register) 40h (the low byte of the address desired) 40h goes into latch but is
not latched yet.
FC00h + 3Eh (offset of Address/Data Register) 41h (the low byte of the address desired) 41h goes into latch but is
not latched yet.
FC00h + 3Fh an A0h (CMD to load the high address byte). This latches the low address through changing the
decode bits and opens the door for the high address latch.
Out
Out
FC00h + 3Eh 00h (the high byte of the address desired) 00h goes into latch but is not latched yet.
FC00h + 3Fh an E0h (CMD to read the address latched). This latches the high address through changing the
decode bits and begins the read NVRAM data operation.
In
In
FC00h + 3Fh until D31 = 0 (not busy).
FC00h + 3Eh the data.
Notes:
1. Latched addresses do not automatically increment after a read or write. They must be loaded with new values.
2. Latched addresses remain after reads and writes. It is allowable to only update one address byte for the next access.
3. A processor may perform a one word write to load an address byte and control command simultaneously.
AMCC Confidential and Proprietary
DS1527
123
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
