12.2.2.1 Single Cycle Pass-Thru Writes ................................................................................ 12-6
12.2.2.2 Single Cycle Pass-Thru Reads ............................................................................... 12-8
12.2.2.3 Pass-Thru Burst Writes ........................................................................................... 12-9
12.2.2.4 Pass-Thru Burst Reads ......................................................................................... 12-13
12.2.2.5 Add-On Pass-Thru Disconnect Operation ............................................................ 12-17
12.2.2.6 8-Bit and 16-Bit Pass-Thru Add-On Bus Interface ................................................. 12-18
12.3 CONFIGURATION ............................................................................................................................ 12-21
12.3.1 S5933 Base Address Register Definition ............................................................................... 12-21
12.3.2 Creating a Pass-Thru Region ................................................................................................ 12-21
12.3.3 Accessing a Pass-Thru Region ............................................................................................. 12-22
13. ELECTRICAL CHARACTERISTICS ............................................................................. 13-1
13.1 ABSOLUTE MAXIMUM RATINGS ...................................................................................................... 13-3
13.2 DC CHARACTERISTICS .................................................................................................................... 13-3
13.2.1 PCI Bus Signals ....................................................................................................................... 13-4
13.2.2 Add-On Bus Signals ................................................................................................................ 13-5
13.3 AC CHARACTERISTICS .................................................................................................................... 13-6
13.3.1 PCI Bus Timings ...................................................................................................................... 13-6
13.3.2 Add-On Bus Timings ................................................................................................................ 13-8
13.3.3 Asynchronous RDFIFO# Timing .............................................................................................. 13-9
13.3.4 Asynchronous WRFIFO# Timing ........................................................................................... 13-10
13.3.5 Synchronous RDFIFO# Timing ............................................................................................... 13-11
13.3.6 Synchronous WRFIFO# Timing ............................................................................................. 13-12
13.3.7 Asynchronous RD# FIFO Timing ........................................................................................... 13-13
13.3.8 Asynchronous WR# FIFO Timing ........................................................................................... 13-14
13.3.9 Synchronous RD# FIFO Timing ............................................................................................. 13-15
13.3.10 Synchronous Multiple RD# FIFO Timing .............................................................................. 13-16
13.3.11 Synchronous WR# FIFO Timing .......................................................................................... 13-17
13.3.12 Synchronous Multiple WR# FIFO Timing ............................................................................. 13-18
13.3.13 Target S5933 Pass-Thru Interface Timings .......................................................................... 13-19
13.3.14 Target Byte-Wide nv Memory Interface Timings .................................................................. 13-21
13.3.15 Target Interrupt Timings ....................................................................................................... 13-23
14. PINOUT AND PACKAGE INFORMATION ..................................................................... 14-1
14.1 S5933 PINOUT AND PIN ASSIGNMENT – 160 PQFP ...................................................................... 14-3
14.2 S5933 PINOUT AND PIN ASSIGNMENT – 208 TQFP ...................................................................... 14-4
14.3 PACKAGE PHYSICAL DIMENSIONS – 160 PQFP ........................................................................... 14-7
14.4 PACKAGE PHYSICAL DIMENSIONS – 208 TQFP .......................................................................... 14-11
14.5 ORDERING INFORMATION ............................................................................................................. 14-12
15. APPLICATION NOTES AND SOFTWARE EXAMPLES ............................................... 15-1
S5933 DEVICE ID ASSIGNMENT PROCEDURE ...................................................................................... 15-3
PCI PCB DESIGN LAYOUT GUIDELINES ................................................................................................. 15-5
BUS MASTERING WITH THE S5933 PCI MATCHMAKER ....................................................................... 15-9
ADD-ON DMA CONTROLLER DESIGN FOR THE S5933 ....................................................................... 15-27
SOFTWARE DEVELOPER’S GUIDE ....................................................................................................... 15-53
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
