5. PCI BUS OPERATION REGISTERS ............................................................................... 5-3
5.1 OUTGOING MAILBOX REGISTERS (OMB) ........................................................................................ 5-4
5.2 INCOMING MAILBOX REGISTERS (IMB) ........................................................................................... 5-4
5.3 FIFO REGISTER PORT (FIFO) ............................................................................................................ 5-4
5.4 PCI CONTROLLED BUS MASTER WRITE ADDRESS REGISTER (MWAR) ..................................... 5-5
5.5 PCI CONTROLLED BUS MASTER WRITE TRANSFER COUNT REGISTER (MWTC)...................... 5-6
5.6 PCI CONTROLLED BUS MASTER READ ADDRESS REGISTER (MRAR) ....................................... 5-7
5.7 PCI CONTROLLED BUS MASTER READ TRANSFER COUNT REGISTER (MRTC) ........................ 5-8
5.8 MAILBOX EMPTY FULL/STATUS REGISTER (MBEF) ........................................................................ 5-9
5.9 INTERRUPT CONTROL/STATUS REGISTER (INTCSR) .................................................................. 5-11
5.10 BUS MASTER CONTROL/STATUS REGISTER (MCSR) .................................................................. 5-15
6. ADD-ON BUS OPERATION REGISTERS....................................................................... 6-3
6.1 ADD-ON INCOMING MAILBOX REGISTERS (AIMBx)........................................................................ 6-4
6.2 ADD-ON OUTGOING MAILBOX REGISTERS (AOMBx)..................................................................... 6-4
6.3 ADD-ON FIFO REGISTER PORT (AFIFO) .......................................................................................... 6-4
6.4 ADD-ON CONTROLLED BUS MASTER WRITE ADDRESS REGISTER (MWAR) ............................. 6-5
6.5 ADD-ON PASS-THRU ADDRESS REGISTER (APTA) ........................................................................ 6-6
6.6 ADD-ON PASS-THRU DATA REGISTER (APTD) ................................................................................ 6-6
6.7 ADD-ON CONTROLLED BUS MASTER READ ADDRESS REGISTER (MRAR) ............................... 6-7
6.8 ADD-ON EMPTY/FULL STATUS REGISTER (AMBEF) ....................................................................... 6-8
6.9 ADD-ON INTERRUPT CONTROL/STATUS REGISTER (AINT) ........................................................ 6-10
6.10 ADD-ON GENERAL CONTROL/STATUS REGISTER (AGCSTS) ..................................................... 6-13
6.11 ADD-ON CONTROLLED BUS MASTER WRITE TRANSFER COUNT REGISTER (MWTC) ........... 6-16
6.12 ADD-ON CONTROLLED BUS MASTER READ TRANSFER COUNT REGISTER (MRTC) .............. 6-17
7. INITIALIZATION............................................................................................................... 7-3
7.1 PCI RESET ........................................................................................................................................... 7-3
7.2 LOADING FROM BYTE-WIDE NV MEMORIES................................................................................... 7-3
7.3 LOADING FROM SERIAL NV MEMORIES .......................................................................................... 7-4
7.4 PCI BUS CONFIGURATION CYCLES ................................................................................................. 7-6
7.5 EXPANSION BIOS ROMS .................................................................................................................... 7-8
8. PCI BUS INTERFACE ..................................................................................................... 8-3
8.1 PCI BUS TRANSACTIONS .................................................................................................................. 8-3
8.1.1 PCI Burst Transfers ................................................................................................................... 8-4
8.1.2 PCI Read Transfers.................................................................................................................... 8-4
8.1.3 PCI Write Transfers .................................................................................................................... 8-6
8.1.4 Master-Initiated Termination ...................................................................................................... 8-7
8.1.4.1 Normal Cycle Completion.......................................................................................... 8-7
8.1.4.2 Initiator Preemption ................................................................................................... 8-8
8.1.4.3 Master Abort.............................................................................................................. 8-9
8.1.5 Target-Initiated Termination ....................................................................................................... 8-9
8.1.5.1 Target Disconnects .................................................................................................. 8-10
8.1.5.2 Target Requested Retries........................................................................................ 8-11
8.1.5.3 Target Aborts ........................................................................................................... 8-11
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
