8.2 PCI BUS MASTERSHIP ..................................................................................................................... 8-13
8.2.1 Bus Mastership Latency Components ..................................................................................... 8-13
8.2.1.1 Bus Arbitration ......................................................................................................... 8-13
8.2.1.2 Bus Acquisition ........................................................................................................ 8-14
8.2.1.3 Target Latency ......................................................................................................... 8-14
8.2.2 Target Locking ......................................................................................................................... 8-14
8.3 PCI BUS INTERRUPTS ...................................................................................................................... 8-16
8.4 PCI BUS PARITY ERRORS................................................................................................................ 8-16
9. ADD-ON BUS INTERFACE ............................................................................................. 9-3
9.1 ADD-ON OPERATION REGISTER ACCESSES .................................................................................. 9-3
9.1.1 Add-On Interface Signals........................................................................................................... 9-3
9.1.1.1 System Signals.......................................................................................................... 9-3
9.1.1.2 Register Access Signals............................................................................................ 9-3
9.1.2 Asynchronous Register Accesses ............................................................................................. 9-4
9.1.3 Synchronous FIFO and Pass-Thru Data Register Accesses..................................................... 9-4
9.1.4 nv Memory Accesses Through the Add-On General Control/Status Register ........................... 9-4
9.2 MAILBOX BUS INTERFACE ................................................................................................................. 9-4
9.2.1 Mailbox Interrupts ...................................................................................................................... 9-7
9.3 FIFO BUS INTERFACE ........................................................................................................................ 9-7
9.3.1 FIFO Direct Access Inputs......................................................................................................... 9-7
9.3.2 FIFO Status Signals .................................................................................................................. 9-7
9.3.3 FIFO Control Signals ................................................................................................................. 9-7
9.4 PASS-THRU BUS INTERFACE ............................................................................................................ 9-7
9.4.1 Pass-Thru Status Indicators ...................................................................................................... 9-8
9.4.2 Pass-Thru Control Inputs........................................................................................................... 9-8
9.5 NON-VOLATILE MEMORY INTERFACE .............................................................................................. 9-8
9.5.1 Non-Volatile Memory Interface Signals...................................................................................... 9-8
9.5.2 Accessing Non-Volatile Memory ................................................................................................ 9-9
9.5.3 nv Memory Device Timing Requirements ................................................................................ 9-11
10. MAILBOX OVERVIEW................................................................................................... 10-3
10.1 FUNCTIONAL DESCRIPTION ........................................................................................................... 10-3
10.1.1 Mailbox Empty/Full Conditions ................................................................................................ 10-4
10.1.2 Mailbox Interrupts .................................................................................................................... 10-4
10.1.3 Add-On Outgoing Mailbox 4, Byte 3 Access............................................................................ 10-4
10.2 BUS INTERFACE ............................................................................................................................... 10-5
10.2.1 PCI Bus Interface .................................................................................................................... 10-5
10.2.2 Add-On Bus Interface .............................................................................................................. 10-5
10.2.2.1 8-Bit and 16-Bit Add-On Interfaces ............................................................................ 10-5
10.3 CONFIGURATION .............................................................................................................................. 10-6
10.3.1 Mailbox Status ......................................................................................................................... 10-6
10.3.2 Mailbox Interrupts .................................................................................................................... 10-7
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
