C
ONTENTS
1.
CORPORATE OVERVIEW .............................................................................................. 1-3
CAPABILITY SUMMARY .............................................................................................................................. 1-3
PRODUCT SELECTION GUIDES ................................................................................................................ 1-5
2.
ARCHITECTURAL OVERVIEW ...................................................................................... 2-3
2.1 PCI AGENT ........................................................................................................................................... 2-6
2.2 ADD-ON INTERFACE ........................................................................................................................... 2-7
2.3 NON-VOLATILE MEMORY INTERFACE .............................................................................................. 2-7
3.
SIGNAL DESCRIPTIONS ................................................................................................ 3-3
3.1 PCI BUS INTERFACE SIGNALS .......................................................................................................... 3-4
3.1.1 Address and Data Pins – PCI Local Bus ................................................................................... 3-4
3.1.2 System Pins – PCI Local Bus .................................................................................................... 3-5
3.1.3 Interface Control Pins – PCI Bus Signal .................................................................................... 3-5
3.1.4 Arbitration Pins (Bus Masters Only) – PCI Local Bus ................................................................ 3-6
3.1.5 Error Reporting Pins – PCI Local Bus ....................................................................................... 3-6
3.1.6 Interrupt Pin – PCI Local Bus .................................................................................................... 3-6
3.2 NON-VOLATILE MEMORY INTERFACE SIGNALS ............................................................................. 3-7
3.2.1 Serial nv Devices ....................................................................................................................... 3-7
3.2.2 Byte-Wide nv Devices ................................................................................................................ 3-7
3.3 ADD-ON BUS INTERFACE SIGNALS .................................................................................................. 3-8
3.3.1 Register Access Pins ................................................................................................................. 3-8
3.3.2 FIFO Access Pins ...................................................................................................................... 3-9
3.3.3 Pass-Thru Interface Pins ........................................................................................................... 3-9
3.3.4 System Pins ............................................................................................................................. 3-10
4.
PCI CONFIGURATION REGISTERS............................................................................... 4-3
4.1 VENDOR IDENTIFICATION REGISTER (VID) ..................................................................................... 4-4
4.2 DEVICE IDENTIFICATION REGISTER (DID) ...................................................................................... 4-5
4.3 PCI COMMAND REGISTER (PCICMD) ............................................................................................... 4-6
4.4 PCI STATUS REGISTER (PCISTS) ...................................................................................................... 4-8
4.5 REVISION IDENTIFICATION REGISTER (RID) ................................................................................. 4-10
4.6 CLASS CODE REGISTER (CLCD) .................................................................................................... 4-11
4.7 CACHE LINE SIZE REGISTER (CALN) ............................................................................................. 4-15
4.8 LATENCY TIMER REGISTER (LAT) ................................................................................................... 4-16
4.9 HEADER TYPE REGISTER (HDR) .................................................................................................... 4-17
4.10 BUILT-IN SELF-TEST REGISTER (BIST) .......................................................................................... 4-18
4.11 BASE ADDRESS REGISTERS (BADR) ............................................................................................. 4-19
4.12 EXPANSION ROM BASE ADDRESS REGISTER (XROM) ................................................................ 4-23
4.13 INTERRUPT LINE REGISTER (INTLN) ............................................................................................. 4-25
4.14 INTERRUPT PIN REGISTER (INTPIN) .............................................................................................. 4-26
4.15 MINIMUM GRANT REGISTER (MINGNT) ........................................................................................ 4-27
4.16 MAXIMUM LATENCY REGISTER (MAXLAT) ..................................................................................... 4-28
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
