S5933Q/7C 参数 Datasheet PDF下载

11. FIFO OVERVIEW ........................................................................................................... 11-1

11.1 FUNCTIONAL DESCRIPTION ............................................................................................................ 11-3

11.1.1 FIFO Buffer Management and Endian Conversion .................................................................. 11-3

11.1.1.1 FIFO Advance Conditions ........................................................................................ 11-3

11.1.1.2 Endian Conversion ................................................................................................... 11-4

11.1.1.3 64-Bit Endian Conversion ......................................................................................... 11-5

11.1.2 Add-On FIFO Status Indicators ................................................................................................ 11-6

11.1.3 Add-On FIFO Control Signals ................................................................................................... 11-6

11.1.4 PCI Bus Mastering with the FIFO ............................................................................................. 11-6

11.1.4.1 Add-On Initiated Bus Mastering ................................................................................ 11-6

11.1.4.2 PCI Initiated Bus Mastering ...................................................................................... 11-7

11.1.4.3 Address and Transfer Count Registers ..................................................................... 11-7

11.1.4.4 Bus Mastering FIFO Management Schemes ........................................................... 11-7

11.1.4.5 FIFO Bus Master Cycle Priority ................................................................................ 11-8

11.1.4.6 FIFO Generated Bus Master Interrupts .................................................................... 11-8

11.2 BUS INTERFACE ................................................................................................................................ 11-8

11.2.1 FIFO PCI Interface (Target Mode) ............................................................................................ 11-8

11.2.2 FIFO PCI Interface (Initiator Mode) .......................................................................................... 11-9

11.2.2.1 FIFO PCI Bus Master Reads .................................................................................. 11-11

11.2.2.2 FIFO PCI Bus Master Writes .................................................................................. 11-11

11.2.3 Add-On Bus Interface ............................................................................................................. 11-11

11.2.3.1 Add-On FIFO Register Accesses ........................................................................... 11-11

11.2.3.2 Add-On FIFO Direct Access Mode ......................................................................... 11-12

11.2.3.3 Additional Status/Control Signals for Add-On Initiated Bus Mastering ................... 11-13

11.2.3.4 FIFO Generated Add-On Interrupts ........................................................................ 11-14

11.2.3.5 8-Bit and 16-Bit FIFO Add-On Interfaces ............................................................... 11-14

11.3 CONFIGURATION ............................................................................................................................. 11-15

11.3.1 FIFO Setup During Initialization .............................................................................................. 11-15

11.3.2 FIFO Status and Control Bits .................................................................................................. 11-15

11.3.3 PCI Initiated FIFO Bus Mastering Setup ................................................................................ 11-16

11.3.4 Add-On Initiated FIFO Bus Mastering Setup .......................................................................... 11-17

12. PASS-THRU OVERVIEW .............................................................................................. 12-1

12.1 FUNCTIONAL DESCRIPTION ...........................................................................................................

12.1.1 Pass-Thru Transfers ................................................................................................................

12.1.2 Pass-Thru Status/Control Signals ...........................................................................................

12.1.3 Pass-Thru Add-On Data Bus Sizing ........................................................................................

12.2 BUS INTERFACE ...............................................................................................................................

12.2.1 PCI Bus Interface ....................................................................................................................

12.2.1.1 PCI Pass-Thru Single Cycle Accesses ....................................................................

12.2.1.2 PCI Pass-Thru Burst Accesses ...............................................................................

12.2.1.3 PCI Retry Conditions ...............................................................................................

12.2.1.4 PCI Write Retries .....................................................................................................

12.2.1.5 PCI Read Retries ....................................................................................................

12.2.2 Add-On Bus Interface ..............................................................................................................

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