Revision 1.02 – April 12, 2007
S5920 – PCI Product: Electrical Characteristics
Data Book
Figures 2 and 3 define the conditions under which timing measurements are made. The user designs must guaran-
tee that minimum timings are met with maximum clock skew rate (fastest edge) and voltage swing.
Figure 84. PCI Signal Output Timing
PCI CLK
1.5
t5
OUTPUT
1.5
DELAY
TRI-STATE
1.5
1.5
OUTPUT
t6
t7
Figure 85. PCI Signal Input Timing
PCI CLK
INPUT
t8
t9
INPUTS VALID
Add-On Signal Timings
AMCC Confidential and Proprietary
DS1596
153