SONET/SDH/ATM OC-3/OC-12 TRANSCEIVER
The timing generator also produces a feedback ref-
erence clock to the clock synthesizer. A counter
divides the synthesized clock down to the same fre-
quency as the Reference Clock REFCLK. The PLL
in the clock synthesizer maintains the stability of the
synthesized clock by comparing the phase of the
internal clock with that of the reference clock
(REFCLK). The modulus of the counter is a function
of the reference clock frequency and the operating
frequency.
S3028
put on the parallel output data bus (POUT[7:0]).
When framing pattern detection is enabled, the
frame boundary is reported on the Frame Pulse (FP)
output when any 48-bit pattern matching the framing
pattern is detected on the incoming data stream.
When framing pattern detection is disabled, the byte
boundary is frozen to the location found when detec-
tion was previously enabled. Only framing patterns
aligned to the fixed byte boundary are indicated on
the FP output.
The probability that random data in an STS-3 or
STS-12 stream will generate the 48-bit framing pat-
tern is extremely small. It is highly improbable that a
mimic pattern would occur within one frame of data.
Therefore, the time to match the first frame pattern
and to verify it with down-stream circuitry, at the next
occurrence of the pattern, is expected to be less
than the required 250
µs,
even for extremely high bit
error rates.
Once down-stream overhead circuitry has verified
that frame and byte synchronization are correct, the
OOF input can be set low to disable the frame
search process from trying to synchronize to a mimic
frame pattern.
Parallel-to-Serial Converter
The parallel-to-serial converter shown in Figure 4 is
comprised of two 8-bit wide registers. The first regis-
ter latches the data from the PIN[7:0] bus on the
rising edge of PICLK. The second register is a paral-
lel loadable shift register which takes its parallel
input from the first register.
An internally generated byte clock, which is phase
aligned to the transmit serial clock as described in
the Timing Generator description, activates the paral-
lel data transfer between registers. The serial data is
shifted out of the second register at the TSCLK rate.
RECEIVER OPERATION
The S3028 transceiver chip provides the first stage
of the digital processing of a receive SONET STS-3
or STS-12 bit-serial stream. It converts the bit-serial
155.52 or 622.08 Mbit/sec data stream into a 19.44,
38.88 or 77.76 Mbyte/sec parallel data format. A
loopback mode is provided for diagnostic loopback
(transmitter to receiver). An additional loopback mode
is provided for line loopback (receiver to transmitter).
Serial to Parallel Converter
The serial to parallel converter consists of three 8-bit
registers. The first is a serial-in, parallel-out shift reg-
ister, which performs serial to parallel conversion
clocked by the clock recovery block. The second is
an 8-bit internal holding register, which transfers
data from the serial to parallel register on byte
boundaries as determined by the frame and byte
boundary detection block. On the falling edge of the
free running POCLK, the data in the holding register
is transferred to an output holding register which
drives POUT[7:0].
The delay through the serial to parallel converter can
vary from 1.5 to 2.5 byte periods (12 to 20 serial bit
periods) measured from the first bit of an incoming
byte to the beginning of the parallel output of that
byte. The variation in the delay is dependent on the
alignment of the internal parallel load timing, which is
synchronized to the data byte boundaries, with re-
spect to the falling edge of POCLK, which is
independent of the byte boundaries. The advantage of
this serial to parallel converter is that POCLK is neither
truncated nor extended during reframe sequences.
Frame and Byte Boundary Detection
The frame and byte boundary detection circuitry
searches the incoming data for three consecutive A1
bytes followed immediately by three consecutive A2
bytes. Framing pattern detection is enabled and dis-
abled by the Out Of Frame (OOF) input. Detection is
enabled by a rising edge on OOF, and remains en-
abled for the duration that OOF is set High. It is
disabled when a framing pattern is detected after
OOF is set Low. When framing pattern detection is
enabled, the framing pattern is used to locate byte
and frame boundaries in the incoming data stream
(RSD or looped transmitter data). The timing genera-
tor block takes the located byte boundary and uses it
to block the incoming data stream into bytes for out-
December 13, 1999 / Revision H
5
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
