S3028
TRANSCEIVER FUNCTIONAL
DESCRIPTION
TRANSMITTER OPERATION
The S3028 transceiver chip performs the serializing
stage in the processing of a transmit SONET STS-3 or
STS-12 bit serial data stream. It converts the 8-bit par-
allel 19.44, 38.88 or 77.76 Mbyte/sec data stream
into bit serial format at 155.52 or 622.08 Mbit/sec.
Diagnostic loopback is provided (transmitter to re-
ceiver). Line loopback is also provided (receiver-to-
transmitter).
A high-frequency bit clock can be generated from a
19.44, 38.88, 51.84 or 77.76 MHz frequency reference
by using an integral frequency synthesizer consisting of
a phase-locked loop circuit with a divider in the loop.
SONET/SDH/ATM OC-3/OC-12 TRANSCEIVER
Table 3. Reference Frequency Options
REFSEL[1:0]
00
01
10
11
Reference Clock
Frequency
19.44 MHz
38.88 MHz
51.84 MHz
77.76 MHz
Operating Mode
STS-12, STS-3
STS-12, STS-3
STS-12, STS-3
STS-12
Table 4. Reference Jitter Limits
Frequency
Band
12 kHz to 5 MHz
12 kHz to 1 MHz
Maximum Reference
Clock Jitter
14 ps rms
56 ps rms
Operating Mode
STS-12
STS-3
Clock Synthesizer
The clock synthesizer, shown in the block diagram in
Figure 4, is a monolithic PLL that generates the
serial output clock phase synchronized with the input
Reference Clock (REFCLK). There are three select-
able output clock frequencies that are synthesizable
from any of four selectable reference frequencies for
SONET/SDH operation.
The MODE inputs select the output serial clock fre-
quency to be 622.08 MHz for STS-12, or 155.52
MHz for STS-3. Their frequencies are selected as
shown in Table 2.
In order to meet the 0.01 UI SONET jitter generation
specifications, the maximum reference clock jitter
must be guaranteed over the 12 kHz to 1 MHz band-
width for the STS-3 operating mode. For details of
reference clock jitter requirements, see Table 4.
The on–chip PLL consists of a phase detector, which
compares the phase relationship between the VCO out-
put and the REFCLK input, a loop filter which converts
the phase detector output into a smooth DC voltage, and
a VCO, whose frequency is varied by this voltage.
The loop filter generates a VCO control voltage based
on the average DC level of the phase discriminator
output pulses. The loop filter’s corner frequency is
optimized to minimize output phase jitter.
Timing Generator
Table 2. Clock Frequency Options
MODE
1
0
Output Clock Frequency
622.08 MHz
155.52 MHz
Operating Mode
STS-12
STS-3
The timing generator function, seen in Figure 4, pro-
vides two separate functions. It provides a byte rate
version of the TSCLK, and a mechanism for aligning
the phase between the incoming byte clock and the
clock which loads the parallel-to-serial shift register.
The PCLK output is a byte rate version of TSCLK.
For STS-12, the PCLK frequency is 77.76 MHz, and
for STS-3, its frequency is 19.44 or 38.88 MHz.
PCLK is intended for use as an 8-bit parallel clock for
upstream multiplexing and overhead processing cir-
cuits. Using PCLK for upstream circuits will ensure a
stable frequency and phase relationship between the
data coming into and leaving the S3028 device.
In the parallel-to-serial conversion process, the in-
coming data is passed from the PICLK 8-bit parallel
clock timing domain to the internally generated serial
clock timing domain, which is phase aligned to
TSCLK.
The REFSEL[1:0] inputs in combination with the MODE
input select the ratio between the output clock fre-
quency and the reference input frequency, as shown
in Table 3. This ratio is adjusted for each of the four
operating modes so that the reference frequency se-
lected by the REFSEL[1:0] is the same for all
modes.
The REFCLK input must be generated from a differ-
ential PECL crystal oscillator which has a frequency
accuracy that meets the value specified in Table 9 in
order for the TSCLK frequency to have the same
accuracy required for operation in a SONET system.
4
December 13, 1999 / Revision H
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
