SONET/SDH/ATM OC-3/OC-12 TRANSCEIVER
Table 5. S3028 Transceiver Pin Assignment and Descriptions (Continued)
Pin Name
FP
Level
TTL
I/O
O
Pin #
35
Description
S3028
Frame Pulse. Indicates frame boundaries in the incoming data
stream (RSD). If framing pattern detection is enabled, as
controlled by the OOF input, FP pulses high for one POCLK
cycle when a 48-bit sequence matching the framing is detected
on the RSD inputs. When framing pattern detection is disabled,
FP pulses high when the incoming data stream, after byte
alignment, matches the framing pattern. FP is updated on the
falling edge of POCLK.
A 77.76, 51.84, 38.88, or 19.44 MHz nominally 50% duty cycle,
byte rate output clock that is aligned to POUT[7:0] byte serial
output data. POUT[7:0] and FP are updated on the falling edge
of POCLK.
POCLK
TTL
O
47
Table 6. S3028 Common Control Pin Assignment and Descriptions
Pin Name
TESTEN
Level
TTL
I/ O
I
Pin #
13
Description
Test Enable. Test clock/loop timing enable signal. Active High.
Set high to provide access to the PLL during production tests.
Also used to enable loop timing mode when High (S3028B only).
Bus Width selection. Used to select 4-bit or 8-bit operation of
the transmit and receive parallel interfaces. Low selects a 4-bit
bus width. High selects an 8-bit bus width. Must be high for
622.08 Mbit/s normal operation (S3028). Low in 622.08 Mbit/s
mode enables squelched clock operation (S3028B only).
Reference Clock input. Used as the reference for the internal bit
clock frequency synthesizer.
Diagnostic Loopback Enable. Active Low. Selects diagnostic
loopback. When DLEB is high, the S3028 device uses the
primary data (RSD) and clock (RSCLK) inputs. When low, the
S3028 device uses the diagnostic loopback clock and data from
the transmitter.
Master Reset. Reset input for the device, active Low. During
reset, PCLK does not toggle.
Line Loopback Enable. Active Low. Selects line loopback. When
LLEB is active, the S3028 will route the data from the
RSD/RSCLK inputs to the TSD/TSCLK outputs.
Reference Select inputs. Used to select the reference clock
frequency. See Table 3.
Mode select, used to select the serial bit rate. Low selects
155.52 Mbit/s. High selects 622.08 Mbit/s. For 155.52 Mbit/s
mode, the parallel interface can operate with 4 bits.
Test Reset input. Active High. Used to reset portions of the PLL
during production testing. Held Low for normal operation.
BUSWIDTH
TTL
I
30
REFCLKP
REFCLKN
DLEB
Diff.
PECL
TTL
I
15
14
32
I
RSTB
TTL
I
48
LLEB
TTL
I
31
REFSEL1
REFSEL0
MODE
TTL
I
4
3
49
TTL
I
TESTRST
TTL
I
50
December 13, 1999 / Revision H
9
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
