®
DEVICE
SPECIFICATION
Now available with
Loop Timing!
SONET/SDH/ATM OC-3/OC-12 TRANSCEIVER
BiCMOS PECL CLOCK GENERATOR
SONET/SDH/ATM OC-12 TRANSMITTER AND RECEIVER
OC-3/OC-12 TRANSCEIVER
GENERAL DESCRIPTION
S3028
S3028
S3028
FEATURES
• Complies with Bellcore and ITU-T
specifications
• Jitter generation better than ITU-T requirements
• On-chip high-frequency PLL for clock
generation
• Supports 155.52 Mbps (OC-3) and
622.08 Mbps (OC-12)
• Selectable reference frequencies of 19.44,
38.88, 51.84, or 77.76 MHz
• Interface to both PECL and TTL logic
• 4-bit or 8-bit OC-3 TTL datapath
• 8-bit OC-12 TTL datapath
• Compact 64 PQFP package
• Diagnostic loopback mode
• Line loopback mode
• Lock detect
• LOS input
• Low jitter PECL interface
• 0.9W typical power dissipation
• Loop Timing (S3028B only)
• Forward Clocking (S3028B only)
• "Squelched Clock" operation (S3028B only)
• 5 V Power supply
The S3028 SONET/SDH transceiver chip is a fully
integrated serialization/deserialization SONET
OC-12 (622.08 Mbit/s) and OC-3 (155.52 Mbit/s) in-
terface device. The chip performs all necessary
serial-to-parallel and parallel-to-serial functions in
conformance with SONET/SDH transmission stan-
dards. The device is suitable for SONET-based ATM
applications and can be used in conjunction with
AMCC’s S3026 Clock Recovery Unit (CRU). Figure
1 shows a typical network application.
On-chip clock synthesis is performed by the high-
frequency phase-locked loop on the S3028
transceiver chip allowing the use of a slower external
transmit clock reference. The S3028 also performs
SONET/SDH frame detection. The chip can be used
with a 19.44, 38.88, 51.84 or 77.76 MHz reference
clock, in support of existing system clocking
schemes.
The low jitter PECL interface guarantees compliance
with the bit-error rate requirements of the Bellcore
and ITU-T standards. The S3028 is packaged in a
64 PQFP, offering designers a small package out-
line.
Since the S3028 jitter generation is better than the
ITU-T requirements over all reference frequencies,
the designer can meet the overall system require-
ment including the optical interface devices (refer to
Table 9 for jitter generation specifications).
APPLICATIONS
•
•
•
•
•
•
•
•
•
SONET/SDH-based transmission systems
SONET/SDH modules
SONET/SDH test equipment
ATM over SONET/SDH
Section repeaters
Add Drop Multiplexers (ADM)
Broad-band cross-connects
Fiber optic terminators
Fiber optic test equipment
Figure 1. System Block Diagram
8
Transceiver
Controller
8
S3028
S3026
Fiber
Optic
Module
Fiber
Optic
Module
S3026
8
Transceiver
Controller
S3028
8
December 13, 1999 / Revision H
1
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
